2870   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitStrictFPComparison()  local
2872   if (VT == MVT::f16 && !FullFP16) {  in emitStrictFPComparison()
2888   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitComparison()  local
2892     if (VT == MVT::f16 && !FullFP16) {  in emitComparison()
2996   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in emitConditionalComparison()  local
3000     if (LHS.getValueType() == MVT::f16 && !FullFP16) {  in emitConditionalComparison()
12109   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in LowerVSETCC()  local
12113   if (!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) {  in LowerVSETCC()
12124   assert((!FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16) ||  in LowerVSETCC()
15006 static bool hasPairwiseAdd(unsigned Opcode, EVT VT, bool FullFP16) {  in hasPairwiseAdd()  argument
15010     return (FullFP16 && VT == MVT::f16) || VT == MVT::f32 || VT == MVT::f64;  in hasPairwiseAdd()
15119   const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();  in performExtractVectorEltCombine()  local
15136       hasPairwiseAdd(N0->getOpcode(), VT, FullFP16) &&  in performExtractVectorEltCombine()