Lines Matching refs:DCI
13971 TargetLowering::DAGCombinerInfo &DCI, in performXorCombine() argument
13973 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
14227 TargetLowering::DAGCombinerInfo &DCI, in performMulCombine() argument
14233 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
14457 TargetLowering::DAGCombinerInfo &DCI, in performFpToIntCombine() argument
14528 TargetLowering::DAGCombinerInfo &DCI, in performFDivCombine() argument
14577 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFDivCombine()
14619 TargetLowering::DAGCombinerInfo &DCI) { in tryCombineToEXTR() argument
14620 SelectionDAG &DAG = DCI.DAG; in tryCombineToEXTR()
14659 TargetLowering::DAGCombinerInfo &DCI) { in tryCombineToBSL() argument
14661 SelectionDAG &DAG = DCI.DAG; in tryCombineToBSL()
14815 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
14817 SelectionDAG &DAG = DCI.DAG; in performORCombine()
14827 if (SDValue Res = tryCombineToEXTR(N, DCI)) in performORCombine()
14830 if (SDValue Res = tryCombineToBSL(N, DCI)) in performORCombine()
14864 TargetLowering::DAGCombinerInfo &DCI) { in performSVEAndCombine() argument
14865 if (DCI.isBeforeLegalizeOps()) in performSVEAndCombine()
14868 SelectionDAG &DAG = DCI.DAG; in performSVEAndCombine()
14955 TargetLowering::DAGCombinerInfo &DCI) { in performANDCombine() argument
14956 SelectionDAG &DAG = DCI.DAG; in performANDCombine()
14968 return performSVEAndCombine(N, DCI); in performANDCombine()
15043 TargetLowering::DAGCombinerInfo &DCI, in performFirstTrueTestVectorCombine() argument
15047 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performFirstTrueTestVectorCombine()
15063 SelectionDAG &DAG = DCI.DAG; in performFirstTrueTestVectorCombine()
15073 TargetLowering::DAGCombinerInfo &DCI, in performLastTrueTestVectorCombine() argument
15077 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performLastTrueTestVectorCombine()
15100 SelectionDAG &DAG = DCI.DAG; in performLastTrueTestVectorCombine()
15106 performExtractVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performExtractVectorEltCombine() argument
15109 if (SDValue Res = performFirstTrueTestVectorCombine(N, DCI, Subtarget)) in performExtractVectorEltCombine()
15111 if (SDValue Res = performLastTrueTestVectorCombine(N, DCI, Subtarget)) in performExtractVectorEltCombine()
15114 SelectionDAG &DAG = DCI.DAG; in performExtractVectorEltCombine()
15177 TargetLowering::DAGCombinerInfo &DCI, in performConcatVectorsCombine() argument
15257 if (DCI.isBeforeLegalizeOps()) in performConcatVectorsCombine()
15345 performExtractSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performExtractSubvectorCombine() argument
15347 if (DCI.isBeforeLegalizeOps()) in performExtractSubvectorCombine()
15368 performInsertSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performInsertSubvectorCombine() argument
15410 TargetLowering::DAGCombinerInfo &DCI, in tryCombineFixedPointConvert() argument
15414 if (DCI.isBeforeLegalizeOps()) in tryCombineFixedPointConvert()
15849 TargetLowering::DAGCombinerInfo &DCI, in performAddSubLongCombine() argument
15851 if (DCI.isBeforeLegalizeOps()) in performAddSubLongCombine()
15991 TargetLowering::DAGCombinerInfo &DCI, in performBuildVectorCombine() argument
16034 TargetLowering::DAGCombinerInfo &DCI, in performAddSubCombine() argument
16048 return performAddSubLongCombine(N, DCI, DAG); in performAddSubCombine()
16059 TargetLowering::DAGCombinerInfo &DCI, in tryCombineLongOpWithDup() argument
16061 if (DCI.isBeforeLegalizeOps()) in tryCombineLongOpWithDup()
16241 TargetLowering::DAGCombinerInfo &DCI, in tryConvertSVEWideCompare() argument
16243 if (DCI.isBeforeLegalize()) in tryConvertSVEWideCompare()
16471 TargetLowering::DAGCombinerInfo &DCI, in performIntrinsicCombine() argument
16473 SelectionDAG &DAG = DCI.DAG; in performIntrinsicCombine()
16513 return tryCombineFixedPointConvert(N, DCI, DAG); in performIntrinsicCombine()
16546 return tryCombineLongOpWithDup(IID, N, DCI, DAG); in performIntrinsicCombine()
16716 return tryConvertSVEWideCompare(N, ISD::SETEQ, DCI, DAG); in performIntrinsicCombine()
16718 return tryConvertSVEWideCompare(N, ISD::SETNE, DCI, DAG); in performIntrinsicCombine()
16720 return tryConvertSVEWideCompare(N, ISD::SETGE, DCI, DAG); in performIntrinsicCombine()
16722 return tryConvertSVEWideCompare(N, ISD::SETGT, DCI, DAG); in performIntrinsicCombine()
16724 return tryConvertSVEWideCompare(N, ISD::SETLT, DCI, DAG); in performIntrinsicCombine()
16726 return tryConvertSVEWideCompare(N, ISD::SETLE, DCI, DAG); in performIntrinsicCombine()
16728 return tryConvertSVEWideCompare(N, ISD::SETUGE, DCI, DAG); in performIntrinsicCombine()
16730 return tryConvertSVEWideCompare(N, ISD::SETUGT, DCI, DAG); in performIntrinsicCombine()
16732 return tryConvertSVEWideCompare(N, ISD::SETULT, DCI, DAG); in performIntrinsicCombine()
16734 return tryConvertSVEWideCompare(N, ISD::SETULE, DCI, DAG); in performIntrinsicCombine()
16755 performSignExtendSetCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performSignExtendSetCCCombine() argument
16795 TargetLowering::DAGCombinerInfo &DCI, in performExtendCombine() argument
16801 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND && in performExtendCombine()
16806 tryCombineLongOpWithDup(Intrinsic::not_intrinsic, ABDNode, DCI, DAG); in performExtendCombine()
16816 return performSignExtendSetCCCombine(N, DCI, DAG); in performExtendCombine()
17142 static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in splitStores() argument
17385 TargetLowering::DAGCombinerInfo &DCI) { in performVectorShiftCombine() argument
17398 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI)) in performVectorShiftCombine()
17424 TargetLowering::DAGCombinerInfo &DCI, in performPostLD1Combine() argument
17426 if (DCI.isBeforeLegalizeOps()) in performPostLD1Combine()
17429 SelectionDAG &DAG = DCI.DAG; in performPostLD1Combine()
17519 DCI.CombineTo(LD, NewResults); in performPostLD1Combine()
17520 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result in performPostLD1Combine()
17521 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register in performPostLD1Combine()
17531 TargetLowering::DAGCombinerInfo &DCI, in performTBISimplification() argument
17535 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in performTBISimplification()
17536 !DCI.isBeforeLegalizeOps()); in performTBISimplification()
17539 DCI.CommitTargetLoweringOpt(TLO); in performTBISimplification()
17568 TargetLowering::DAGCombinerInfo &DCI, in performSTORECombine() argument
17580 if (DCI.isBeforeLegalizeOps() && Value.getOpcode() == ISD::FP_ROUND && in performSTORECombine()
17589 if (SDValue Split = splitStores(N, DCI, DAG, Subtarget)) in performSTORECombine()
17593 performTBISimplification(N->getOperand(2), DCI, DAG)) in performSTORECombine()
17603 TargetLowering::DAGCombinerInfo &DCI, in performMSTORECombine() argument
17757 SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) { in performMaskedGatherScatterCombine() argument
17761 if (!DCI.isBeforeLegalize()) in performMaskedGatherScatterCombine()
17795 TargetLowering::DAGCombinerInfo &DCI, in performNEONPostLDSTCombine() argument
17797 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in performNEONPostLDSTCombine()
17922 DCI.CombineTo(N, NewResults); in performNEONPostLDSTCombine()
17923 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); in performNEONPostLDSTCombine()
18113 TargetLowering::DAGCombinerInfo &DCI, in performCONDCombine() argument
18187 TargetLowering::DAGCombinerInfo &DCI, in performBRCONDCombine() argument
18196 if (SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3)) in performBRCONDCombine()
18243 DCI.CombineTo(N, BR, false); in performBRCONDCombine()
18291 TargetLowering::DAGCombinerInfo &DCI, in performCSELCombine() argument
18302 return performCONDCombine(N, DCI, DAG, 2, 3); in performCSELCombine()
18354 TargetLowering::DAGCombinerInfo &DCI, in performSETCCCombine() argument
18400 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performSETCCCombine()
18419 TargetLowering::DAGCombinerInfo &DCI, in performFlagSettingCombine() argument
18428 SDValue Res = DCI.DAG.getNode(GenericOpcode, DL, VT, N->ops()); in performFlagSettingCombine()
18429 return DCI.DAG.getMergeValues({Res, DCI.DAG.getConstant(0, DL, MVT::i32)}, in performFlagSettingCombine()
18434 if (SDNode *Generic = DCI.DAG.getNodeIfExists( in performFlagSettingCombine()
18435 GenericOpcode, DCI.DAG.getVTList(VT), {LHS, RHS})) in performFlagSettingCombine()
18436 DCI.CombineTo(Generic, SDValue(N, 0)); in performFlagSettingCombine()
18480 performSetccMergeZeroCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in performSetccMergeZeroCombine() argument
18484 SelectionDAG &DAG = DCI.DAG; in performSetccMergeZeroCombine()
18512 if (DCI.isAfterLegalizeDAG()) in performSetccMergeZeroCombine()
18600 TargetLowering::DAGCombinerInfo &DCI, in performTBZCombine() argument
18740 TargetLowering::DAGCombinerInfo &DCI) { in performSelectCombine() argument
18741 SelectionDAG &DAG = DCI.DAG; in performSelectCombine()
18781 assert(DCI.isBeforeLegalize() || in performSelectCombine()
18803 TargetLowering::DAGCombinerInfo &DCI) { in performDUPCombine() argument
18807 if (VT.is64BitVector() && DCI.isAfterLegalizeDAG()) { in performDUPCombine()
18808 EVT LVT = VT.getDoubleNumVectorElementsVT(*DCI.DAG.getContext()); in performDUPCombine()
18809 if (SDNode *LN = DCI.DAG.getNodeIfExists( in performDUPCombine()
18810 N->getOpcode(), DCI.DAG.getVTList(LVT), {N->getOperand(0)})) { in performDUPCombine()
18812 return DCI.DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SDValue(LN, 0), in performDUPCombine()
18813 DCI.DAG.getConstant(0, DL, MVT::i64)); in performDUPCombine()
18817 return performPostLD1Combine(N, DCI, false); in performDUPCombine()
19135 performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performSignExtendInRegCombine() argument
19171 if (DCI.isBeforeLegalizeOps()) in performSignExtendInRegCombine()
19257 DCI.CombineTo(N, ExtLoad); in performSignExtendInRegCombine()
19258 DCI.CombineTo(Src.getNode(), ExtLoad, ExtLoad.getValue(1)); in performSignExtendInRegCombine()
19371 performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in performInsertVectorEltCombine() argument
19375 return performPostLD1Combine(N, DCI, true); in performInsertVectorEltCombine()
19401 TargetLowering::DAGCombinerInfo &DCI, in performFPExtendCombine() argument
19413 if (DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(N0.getNode()) && in performFPExtendCombine()
19421 DCI.CombineTo(N, ExtLoad); in performFPExtendCombine()
19422 DCI.CombineTo(N0.getNode(), in performFPExtendCombine()
19493 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
19494 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
19501 return performAddSubCombine(N, DCI, DAG); in PerformDAGCombine()
19503 return performBuildVectorCombine(N, DCI, DAG); in PerformDAGCombine()
19505 return performFlagSettingCombine(N, DCI, ISD::AND); in PerformDAGCombine()
19515 return performFlagSettingCombine(N, DCI, AArch64ISD::ADC); in PerformDAGCombine()
19519 return performFlagSettingCombine(N, DCI, AArch64ISD::SBC); in PerformDAGCombine()
19521 return performXorCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
19523 return performMulCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
19531 return performFpToIntCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
19533 return performFDivCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
19535 return performORCombine(N, DCI, Subtarget); in PerformDAGCombine()
19537 return performANDCombine(N, DCI); in PerformDAGCombine()
19539 return performIntrinsicCombine(N, DCI, Subtarget); in PerformDAGCombine()
19543 return performExtendCombine(N, DCI, DAG); in PerformDAGCombine()
19545 return performSignExtendInRegCombine(N, DCI, DAG); in PerformDAGCombine()
19547 return performConcatVectorsCombine(N, DCI, DAG); in PerformDAGCombine()
19549 return performExtractSubvectorCombine(N, DCI, DAG); in PerformDAGCombine()
19551 return performInsertSubvectorCombine(N, DCI, DAG); in PerformDAGCombine()
19553 return performSelectCombine(N, DCI); in PerformDAGCombine()
19555 return performVSelectCombine(N, DCI.DAG); in PerformDAGCombine()
19557 return performSETCCCombine(N, DCI, DAG); in PerformDAGCombine()
19559 if (performTBISimplification(N->getOperand(1), DCI, DAG)) in PerformDAGCombine()
19563 return performSTORECombine(N, DCI, DAG, Subtarget); in PerformDAGCombine()
19565 return performMSTORECombine(N, DCI, DAG, Subtarget); in PerformDAGCombine()
19568 return performMaskedGatherScatterCombine(N, DCI, DAG); in PerformDAGCombine()
19572 return performFPExtendCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
19574 return performBRCONDCombine(N, DCI, DAG); in PerformDAGCombine()
19577 return performTBZCombine(N, DCI, DAG); in PerformDAGCombine()
19579 return performCSELCombine(N, DCI, DAG); in PerformDAGCombine()
19581 return performDUPCombine(N, DCI); in PerformDAGCombine()
19594 return performSetccMergeZeroCombine(N, DCI); in PerformDAGCombine()
19612 return performVectorShiftCombine(N, *this, DCI); in PerformDAGCombine()
19619 return performInsertVectorEltCombine(N, DCI); in PerformDAGCombine()
19621 return performExtractVectorEltCombine(N, DCI, Subtarget); in PerformDAGCombine()
19623 return performVecReduceAddCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
19628 return tryCombineLongOpWithDup(Intrinsic::not_intrinsic, N, DCI, DAG); in PerformDAGCombine()
19670 return performNEONPostLDSTCombine(N, DCI, DAG); in PerformDAGCombine()