Lines Matching refs:CCVal
3505 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32); in LowerXOR() local
3507 CCVal, Overflow); in LowerXOR()
3549 SDValue CCVal; in LowerXOR() local
3550 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); in LowerXOR()
3557 CCVal, Cmp); in LowerXOR()
3645 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32); in LowerXALUO() local
3647 CCVal, Overflow); in LowerXALUO()
5345 SDValue CCVal = DAG.getConstant(CC, dl, MVT::i32); in LowerBRCOND() local
5346 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBRCOND()
7626 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32); in LowerBR_CC() local
7628 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
7693 SDValue CCVal; in LowerBR_CC() local
7694 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); in LowerBR_CC()
7695 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
8032 SDValue CCVal; in LowerSETCC() local
8034 LHS, RHS, ISD::getSetCCInverse(CC, LHS.getValueType()), CCVal, DAG, dl); in LowerSETCC()
8039 SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp); in LowerSETCC()
8235 SDValue CCVal; in LowerSELECT_CC() local
8236 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); in LowerSELECT_CC()
8238 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp); in LowerSELECT_CC()
8339 SDValue CCVal = Op->getOperand(0); in LowerSELECT() local
8346 SDValue TruncCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, CCVal); in LowerSELECT()
8358 SDValue SplatVal = DAG.getSExtOrTrunc(CCVal, DL, SplatValVT); in LowerSELECT()
8365 if (ISD::isOverflowIntrOpRes(CCVal)) { in LowerSELECT()
8367 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0))) in LowerSELECT()
8372 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG); in LowerSELECT()
8373 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32); in LowerSELECT() local
8376 CCVal, Overflow); in LowerSELECT()
8382 if (CCVal.getOpcode() == ISD::SETCC) { in LowerSELECT()
8383 LHS = CCVal.getOperand(0); in LowerSELECT()
8384 RHS = CCVal.getOperand(1); in LowerSELECT()
8385 CC = cast<CondCodeSDNode>(CCVal.getOperand(2))->get(); in LowerSELECT()
8387 LHS = CCVal; in LowerSELECT()
8388 RHS = DAG.getConstant(0, DL, CCVal.getValueType()); in LowerSELECT()
14006 SDValue CCVal; in BuildSDIVPow2() local
14007 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL); in BuildSDIVPow2()
14009 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp); in BuildSDIVPow2()
14056 SDValue CCVal, CSNeg; in BuildSREMPow2() local
14058 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETGE, CCVal, DAG, DL); in BuildSREMPow2()
14060 CSNeg = DAG.getNode(AArch64ISD::CSNEG, DL, VT, And, And, CCVal, Cmp); in BuildSREMPow2()
14065 SDValue CCVal = DAG.getConstant(AArch64CC::MI, DL, MVT_CC); in BuildSREMPow2() local
14071 CSNeg = DAG.getNode(AArch64ISD::CSNEG, DL, VT, AndPos, AndNeg, CCVal, in BuildSREMPow2()
15640 SDValue CCVal; in performSetccAddFolding() local
15644 CCVal = DAG.getConstant( in performSetccAddFolding()
15651 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, CmpVT), CCVal, DAG, in performSetccAddFolding()
15656 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp); in performSetccAddFolding()
15765 SDValue CCVal = DAG.getConstant(AArch64CC, DL, MVT::i32); in performAddCSelIntoCSinc() local
15768 return DAG.getNode(AArch64ISD::CSINC, DL, VT, NewNode, RHS, CCVal, Cmp); in performAddCSelIntoCSinc()
18200 SDValue CCVal = N->getOperand(2); in performBRCONDCombine() local
18203 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!"); in performBRCONDCombine()
18204 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue(); in performBRCONDCombine()