284 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,  in AArch64TargetLowering()  function in AArch64TargetLowering
1453 void AArch64TargetLowering::addTypeForNEON(MVT VT) {  in addTypeForNEON()
1562 bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,  in shouldExpandGetActiveLaneMask()
1582 void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {  in addTypeForFixedLengthSVE()
1715 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {  in addDRTypeForNEON()
1720 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {  in addQRTypeForNEON()
1725 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &,  in getSetCCResultType()
1829 bool AArch64TargetLowering::targetShrinkDemandedConstant(  in targetShrinkDemandedConstant()
1874 void AArch64TargetLowering::computeKnownBitsForTargetNode(  in computeKnownBitsForTargetNode()
1978 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,  in getScalarShiftAmountTy()
1983 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(  in allowsMisalignedMemoryAccesses()
2008 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(  in allowsMisalignedMemoryAccesses()
2034 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,  in createFastISel()
2039 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
2339 AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,  in EmitF128CSEL()
2398 MachineBasicBlock *AArch64TargetLowering::EmitLoweredCatchRet(  in EmitLoweredCatchRet()
2407 AArch64TargetLowering::EmitTileLoad(unsigned Opc, unsigned BaseReg,  in EmitTileLoad()
2425 AArch64TargetLowering::EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const {  in EmitFill()
2441 AArch64TargetLowering::EmitMopa(unsigned Opc, unsigned BaseReg,  in EmitMopa()
2458 AArch64TargetLowering::EmitInsertVectorToTile(unsigned Opc, unsigned BaseReg,  in EmitInsertVectorToTile()
2476 AArch64TargetLowering::EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const {  in EmitZero()
2493 AArch64TargetLowering::EmitAddVectorToTile(unsigned Opc, unsigned BaseReg,  in EmitAddVectorToTile()
2509 MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(  in EmitInstrWithCustomInserter()
3480 SDValue AArch64TargetLowering::LowerXOR(SDValue Op, SelectionDAG &DAG) const {  in LowerXOR()
3684 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,  in LowerFP_EXTEND()
3697 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,  in LowerFP_ROUND()
3721 SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op,  in LowerVectorFP_TO_INT()
3808 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,  in LowerFP_TO_INT()
3840 AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,  in LowerVectorFP_TO_INT_SAT()
3908 SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,  in LowerFP_TO_INT_SAT()
3964 SDValue AArch64TargetLowering::LowerVectorINT_TO_FP(SDValue Op,  in LowerVectorINT_TO_FP()
4036 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,  in LowerINT_TO_FP()
4071 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,  in LowerFSINCOS()
4107 SDValue AArch64TargetLowering::LowerBITCAST(SDValue Op,  in LowerBITCAST()
4272 SDValue AArch64TargetLowering::LowerFLT_ROUNDS_(SDValue Op,  in LowerFLT_ROUNDS_()
4295 SDValue AArch64TargetLowering::LowerSET_ROUNDING(SDValue Op,  in LowerSET_ROUNDING()
4339 SDValue AArch64TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {  in LowerMUL()
4462 SDValue AArch64TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,  in LowerINTRINSIC_W_CHAIN()
4504 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,  in LowerINTRINSIC_WO_CHAIN()
4844 bool AArch64TargetLowering::shouldExtendGSIndex(EVT VT, EVT &EltTy) const {  in shouldExtendGSIndex()
4853 bool AArch64TargetLowering::shouldRemoveExtendFromGSIndex(EVT IndexVT,  in shouldRemoveExtendFromGSIndex()
4868 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {  in isVectorLoadExtDesirable()
4920 SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,  in LowerMGATHER()
5019 SDValue AArch64TargetLowering::LowerMSCATTER(SDValue Op,  in LowerMSCATTER()
5100 SDValue AArch64TargetLowering::LowerMLOAD(SDValue Op, SelectionDAG &DAG) const {  in LowerMLOAD()
5163 SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,  in LowerSTORE()
5241 SDValue AArch64TargetLowering::LowerStore128(SDValue Op,  in LowerStore128()
5265 SDValue AArch64TargetLowering::LowerLOAD(SDValue Op,  in LowerLOAD()
5319 SDValue AArch64TargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {  in LowerABS()
5353 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
5628 bool AArch64TargetLowering::mergeStoresAfterLegalization(EVT VT) const {  in mergeStoresAfterLegalization()
5632 bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(  in useSVEForFixedLengthVectorVT()
5696 bool AArch64TargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0,  in isReassocProfitable()
5713 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,  in CCAssignFnForCall()
5748 AArch64TargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {  in CCAssignFnForReturn()
5753 SDValue AArch64TargetLowering::LowerFormalArguments(  in LowerFormalArguments()
6075 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,  in saveVarArgRegisters()
6158 SDValue AArch64TargetLowering::LowerCallResult(  in LowerCallResult()
6235 static void analyzeCallOperands(const AArch64TargetLowering &TLI,  in analyzeCallOperands()
6279 bool AArch64TargetLowering::isEligibleForTailCallOptimization(  in isEligibleForTailCallOptimization()
6425 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,  in addTokenForArgument()
6456 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,  in DoesCalleeRestoreStack()
6477 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
6968 bool AArch64TargetLowering::CanLowerReturn(  in CanLowerReturn()
6978 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,  in LowerReturn()
7090 SDValue AArch64TargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,  in getTargetNode()
7097 SDValue AArch64TargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,  in getTargetNode()
7103 SDValue AArch64TargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,  in getTargetNode()
7110 SDValue AArch64TargetLowering::getTargetNode(BlockAddressSDNode* N, EVT Ty,  in getTargetNode()
7118 SDValue AArch64TargetLowering::getGOT(NodeTy *N, SelectionDAG &DAG,  in getGOT()
7131 SDValue AArch64TargetLowering::getAddrLarge(NodeTy *N, SelectionDAG &DAG,  in getAddrLarge()
7147 SDValue AArch64TargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,  in getAddr()
7161 SDValue AArch64TargetLowering::getAddrTiny(NodeTy *N, SelectionDAG &DAG,  in getAddrTiny()
7170 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,  in LowerGlobalAddress()
7231 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,  in LowerDarwinGlobalTLSAddress()
7283 SDValue AArch64TargetLowering::LowerELFTLSLocalExec(const GlobalValue *GV,  in LowerELFTLSLocalExec()
7389 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,  in LowerELFTLSDescCallSeq()
7405 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,  in LowerELFGlobalTLSAddress()
7492 AArch64TargetLowering::LowerWindowsGlobalTLSAddress(SDValue Op,  in LowerWindowsGlobalTLSAddress()
7550 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,  in LowerGlobalTLSAddress()
7582 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {  in LowerBR_CC()
7719 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,  in LowerFCOPYSIGN()
7805 SDValue AArch64TargetLowering::LowerCTPOP_PARITY(SDValue Op,  in LowerCTPOP_PARITY()
7888 SDValue AArch64TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {  in LowerCTTZ()
7899 SDValue AArch64TargetLowering::LowerMinMax(SDValue Op,  in LowerMinMax()
7946 SDValue AArch64TargetLowering::LowerBitreverse(SDValue Op,  in LowerBitreverse()
7996 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {  in LowerSETCC()
8084 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,  in LowerSELECT_CC()
8286 SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op,  in LowerVECTOR_SPLICE()
8326 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,  in LowerSELECT_CC()
8337 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,  in LowerSELECT()
8394 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,  in LowerJumpTable()
8409 SDValue AArch64TargetLowering::LowerBR_JT(SDValue Op,  in LowerBR_JT()
8428 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,  in LowerConstantPool()
8445 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,  in LowerBlockAddress()
8457 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,  in LowerDarwin_VASTART()
8471 SDValue AArch64TargetLowering::LowerWin64_VASTART(SDValue Op,  in LowerWin64_VASTART()
8486 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,  in LowerAAPCS_VASTART()
8565 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,  in LowerVASTART()
8577 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,  in LowerVACOPY()
8596 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {  in LowerVAARG()
8665 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,  in LowerFRAMEADDR()
8686 SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,  in LowerSPONENTRY()
8701 Register AArch64TargetLowering::
8716 SDValue AArch64TargetLowering::LowerADDROFRETURNADDR(SDValue Op,  in LowerADDROFRETURNADDR()
8730 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,  in LowerRETURNADDR()
8771 SDValue AArch64TargetLowering::LowerShiftParts(SDValue Op,  in LowerShiftParts()
8778 bool AArch64TargetLowering::isOffsetFoldingLegal(  in isOffsetFoldingLegal()
8785 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,  in isFPImmLegal()
8851 AArch64TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG,  in getSqrtInputTest()
8861 AArch64TargetLowering::getSqrtResultForDenormInput(SDValue Op,  in getSqrtResultForDenormInput()
8866 SDValue AArch64TargetLowering::getSqrtEstimate(SDValue Operand,  in getSqrtEstimate()
8899 SDValue AArch64TargetLowering::getRecipEstimate(SDValue Operand,  in getRecipEstimate()
8953 const char *AArch64TargetLowering::LowerXConstraint(EVT ConstraintVT) const {  in LowerXConstraint()
8992 AArch64TargetLowering::ConstraintType
8993 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {  in getConstraintType()
9029 AArch64TargetLowering::getSingleConstraintMatchWeight(  in getSingleConstraintMatchWeight()
9061 AArch64TargetLowering::getRegForInlineAsmConstraint(  in getRegForInlineAsmConstraint()
9157 EVT AArch64TargetLowering::getAsmOperandValueType(const DataLayout &DL,  in getAsmOperandValueType()
9168 void AArch64TargetLowering::LowerAsmOperandForConstraint(  in LowerAsmOperandForConstraint()
9354 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,  in ReconstructShuffle()
10450 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,  in LowerVECTOR_SHUFFLE()
10623 SDValue AArch64TargetLowering::LowerSPLAT_VECTOR(SDValue Op,  in LowerSPLAT_VECTOR()
10654 SDValue AArch64TargetLowering::LowerDUPQLane(SDValue Op,  in LowerDUPQLane()
11022 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,  in LowerVectorOR()
11140 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,  in LowerBUILD_VECTOR()
11472 SDValue AArch64TargetLowering::LowerCONCAT_VECTORS(SDValue Op,  in LowerCONCAT_VECTORS()
11508 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,  in LowerINSERT_VECTOR_ELT()
11562 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,  in LowerEXTRACT_VECTOR_ELT()
11614 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,  in LowerEXTRACT_SUBVECTOR()
11660 SDValue AArch64TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op,  in LowerINSERT_SUBVECTOR()
11782 SDValue AArch64TargetLowering::LowerDIV(SDValue Op, SelectionDAG &DAG) const {  in LowerDIV()
11831 bool AArch64TargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {  in isShuffleMaskLegal()
11860 bool AArch64TargetLowering::isVectorClearMaskLegal(ArrayRef<int> M,  in isVectorClearMaskLegal()
11908 SDValue AArch64TargetLowering::LowerTRUNCATE(SDValue Op,  in LowerTRUNCATE()
11931 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,  in LowerVectorSRA_SRL_SHL()
12087 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,  in LowerVSETCC()
12164 SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,  in LowerVECREDUCE()
12241 SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op,  in LowerATOMIC_LOAD_SUB()
12258 SDValue AArch64TargetLowering::LowerATOMIC_LOAD_AND(SDValue Op,  in LowerATOMIC_LOAD_AND()
12275 SDValue AArch64TargetLowering::LowerWindowsDYNAMIC_STACKALLOC(  in LowerWindowsDYNAMIC_STACKALLOC()
12304 AArch64TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,  in LowerDYNAMIC_STACKALLOC()
12349 SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op,  in LowerVSCALE()
12363 setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL,  in setInfoSVEStN()
12364               AArch64TargetLowering::IntrinsicInfo &Info, const CallInst &CI) {  in setInfoSVEStN()
12388 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
12530 bool AArch64TargetLowering::shouldReduceLoadWidth(SDNode *Load,  in shouldReduceLoadWidth()
12565 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {  in isTruncateFree()
12572 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {  in isTruncateFree()
12583 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {  in isProfitableToHoist()
12609 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {  in isZExtFree()
12616 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {  in isZExtFree()
12624 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
12639 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {  in isExtFreeImpl()
12776 bool AArch64TargetLowering::shouldSinkOperands(  in shouldSinkOperands()
12934 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,  in hasPairedLoad()
12947 unsigned AArch64TargetLowering::getNumInterleavedAccesses(  in getNumInterleavedAccesses()
12954 AArch64TargetLowering::getTargetMMOFlags(const Instruction &I) const {  in getTargetMMOFlags()
12961 bool AArch64TargetLowering::isLegalInterleavedAccessType(  in isLegalInterleavedAccessType()
13030 bool AArch64TargetLowering::lowerInterleavedLoad(  in lowerInterleavedLoad()
13203 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,  in lowerInterleavedStore()
13378 SDValue AArch64TargetLowering::LowerSVEStructLoad(unsigned Intrinsic,  in LowerSVEStructLoad()
13413 EVT AArch64TargetLowering::getOptimalMemOpType(  in getOptimalMemOpType()
13443 LLT AArch64TargetLowering::getOptimalMemOpLLT(  in getOptimalMemOpLLT()
13474 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {  in isLegalAddImmediate()
13492 bool AArch64TargetLowering::isMulAddWithConstProfitable(  in isMulAddWithConstProfitable()
13518 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {  in isLegalICmpImmediate()
13524 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
13581 bool AArch64TargetLowering::shouldConsiderGEPOffsetSplit() const {  in shouldConsiderGEPOffsetSplit()
13586 InstructionCost AArch64TargetLowering::getScalingFactorCost(  in getScalingFactorCost()
13602 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(  in isFMAFasterThanFMulAndFAdd()
13622 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F,  in isFMAFasterThanFMulAndFAdd()
13633 bool AArch64TargetLowering::generateFMAsInMachineCombiner(  in generateFMAsInMachineCombiner()
13640 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {  in getScratchRegisters()
13651 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,  in isDesirableToCommuteWithShift()
13673 bool AArch64TargetLowering::isDesirableToCommuteXorWithShift(  in isDesirableToCommuteXorWithShift()
13697 bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(  in shouldFoldConstantShiftPairToMask()
13719 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,  in shouldConvertConstantLoadToIntImm()
13742 bool AArch64TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,  in isExtractSubvectorCheap()
13980 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,  in BuildSDIVPow2()
14029 AArch64TargetLowering::BuildSREMPow2(SDNode *N, const APInt &Divisor,  in BuildSREMPow2()
17384                                          const AArch64TargetLowering &TLI,  in performVectorShiftCombine()
19492 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
19880 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,  in isUsedByReturnOnly()
19917 bool AArch64TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {  in mayBeEmittedAsTailCall()
19921 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,  in getIndexedAddressParts()
19945 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,  in getPreIndexedAddressParts()
19967 bool AArch64TargetLowering::getPostIndexedAddressParts(  in getPostIndexedAddressParts()
19992 void AArch64TargetLowering::ReplaceBITCASTResults(  in ReplaceBITCASTResults()
20098 void AArch64TargetLowering::ReplaceExtractSubVectorResults(  in ReplaceExtractSubVectorResults()
20237 void AArch64TargetLowering::ReplaceNodeResults(  in ReplaceNodeResults()
20367 bool AArch64TargetLowering::useLoadStackGuardNode() const {  in useLoadStackGuardNode()
20373 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {  in combineRepeatedFPDivisors()
20380 AArch64TargetLowering::getPreferredVectorAction(MVT VT) const {  in getPreferredVectorAction()
20392 bool AArch64TargetLowering::isOpSuitableForLDPSTP(const Instruction *I) const {  in isOpSuitableForLDPSTP()
20407 bool AArch64TargetLowering::shouldInsertFencesForAtomic(  in shouldInsertFencesForAtomic()
20416 AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {  in shouldExpandAtomicStoreInIR()
20427 AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {  in shouldExpandAtomicLoadInIR()
20446 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {  in shouldExpandAtomicRMWInIR()
20486 AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(  in shouldExpandAtomicCmpXchgInIR()
20508 Value *AArch64TargetLowering::emitLoadLinked(IRBuilderBase &Builder,  in emitLoadLinked()
20548 void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(  in emitAtomicCmpXchgNoStoreLLBalance()
20554 Value *AArch64TargetLowering::emitStoreConditional(IRBuilderBase &Builder,  in emitStoreConditional()
20593 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(  in functionArgumentNeedsConsecutiveRegisters()
20607 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,  in shouldNormalizeToSelectSequence()
20622 Value *AArch64TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {  in getIRStackGuard()
20637 void AArch64TargetLowering::insertSSPDeclarations(Module &M) const {  in insertSSPDeclarations()
20657 Value *AArch64TargetLowering::getSDagStackGuard(const Module &M) const {  in getSDagStackGuard()
20664 Function *AArch64TargetLowering::getSSPStackGuardCheck(const Module &M) const {  in getSSPStackGuardCheck()
20672 AArch64TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {  in getSafeStackPointerLocation()
20687 bool AArch64TargetLowering::isMaskAndCmp0FoldingBeneficial(  in isMaskAndCmp0FoldingBeneficial()
20700 bool AArch64TargetLowering::
20713 bool AArch64TargetLowering::shouldExpandShift(SelectionDAG &DAG,  in shouldExpandShift()
20721 void AArch64TargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {  in initializeSplitCSR()
20727 void AArch64TargetLowering::insertCopiesSplitCSR(  in insertCopiesSplitCSR()
20768 bool AArch64TargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {  in isIntDivCheap()
20780 bool AArch64TargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {  in preferIncOfAddToSubOfNot()
20785 bool AArch64TargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,  in shouldConvertFpToSat()
20794 bool AArch64TargetLowering::enableAggressiveFMAFusion(EVT VT) const {  in enableAggressiveFMAFusion()
20799 AArch64TargetLowering::getVaListSizeInBits(const DataLayout &DL) const {  in getVaListSizeInBits()
20806 void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {  in finalizeLowering()
20830 bool AArch64TargetLowering::needsFixedCatchObjects() const {  in needsFixedCatchObjects()
20834 bool AArch64TargetLowering::shouldLocalize(  in shouldLocalize()
20857 bool AArch64TargetLowering::fallBackToDAGISel(const Instruction &Inst) const {  in fallBackToDAGISel()
20981 SDValue AArch64TargetLowering::LowerFixedLengthVectorLoadToSVE(  in LowerFixedLengthVectorLoadToSVE()
21037 SDValue AArch64TargetLowering::LowerFixedLengthVectorMLoadToSVE(  in LowerFixedLengthVectorMLoadToSVE()
21080 SDValue AArch64TargetLowering::LowerFixedLengthVectorStoreToSVE(  in LowerFixedLengthVectorStoreToSVE()
21109 SDValue AArch64TargetLowering::LowerFixedLengthVectorMStoreToSVE(  in LowerFixedLengthVectorMStoreToSVE()
21126 SDValue AArch64TargetLowering::LowerFixedLengthVectorIntDivideToSVE(  in LowerFixedLengthVectorIntDivideToSVE()
21201 SDValue AArch64TargetLowering::LowerFixedLengthVectorIntExtendToSVE(  in LowerFixedLengthVectorIntExtendToSVE()
21237 SDValue AArch64TargetLowering::LowerFixedLengthVectorTruncateToSVE(  in LowerFixedLengthVectorTruncateToSVE()
21273 SDValue AArch64TargetLowering::LowerFixedLengthExtractVectorElt(  in LowerFixedLengthExtractVectorElt()
21286 SDValue AArch64TargetLowering::LowerFixedLengthInsertVectorElt(  in LowerFixedLengthInsertVectorElt()
21305 SDValue AArch64TargetLowering::LowerToPredicatedOp(SDValue Op,  in LowerToPredicatedOp()
21362 SDValue AArch64TargetLowering::LowerToScalableOp(SDValue Op,  in LowerToScalableOp()
21390 SDValue AArch64TargetLowering::LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp,  in LowerVECREDUCE_SEQ_FADD()
21418 SDValue AArch64TargetLowering::LowerPredReductionToSVE(SDValue ReduceOp,  in LowerPredReductionToSVE()
21461 SDValue AArch64TargetLowering::LowerReductionToSVE(unsigned Opcode,  in LowerReductionToSVE()
21495 AArch64TargetLowering::LowerFixedLengthVectorSelectToSVE(SDValue Op,  in LowerFixedLengthVectorSelectToSVE()
21519 SDValue AArch64TargetLowering::LowerFixedLengthVectorSetccToSVE(  in LowerFixedLengthVectorSetccToSVE()
21544 AArch64TargetLowering::LowerFixedLengthBitcastToSVE(SDValue Op,  in LowerFixedLengthBitcastToSVE()
21558 SDValue AArch64TargetLowering::LowerFixedLengthConcatVectorsToSVE(  in LowerFixedLengthConcatVectorsToSVE()
21593 AArch64TargetLowering::LowerFixedLengthFPExtendToSVE(SDValue Op,  in LowerFixedLengthFPExtendToSVE()
21618 AArch64TargetLowering::LowerFixedLengthFPRoundToSVE(SDValue Op,  in LowerFixedLengthFPRoundToSVE()
21642 AArch64TargetLowering::LowerFixedLengthIntToFPToSVE(SDValue Op,  in LowerFixedLengthIntToFPToSVE()
21687 AArch64TargetLowering::LowerFixedLengthFPToIntToSVE(SDValue Op,  in LowerFixedLengthFPToIntToSVE()
21730 SDValue AArch64TargetLowering::LowerFixedLengthVECTOR_SHUFFLEToSVE(  in LowerFixedLengthVECTOR_SHUFFLEToSVE()
21854 SDValue AArch64TargetLowering::getSVESafeBitCast(EVT VT, SDValue Op,  in getSVESafeBitCast()
21896 bool AArch64TargetLowering::isAllActivePredicate(SelectionDAG &DAG,  in isAllActivePredicate()
21901 EVT AArch64TargetLowering::getPromotedVTForPredicate(EVT VT) const {  in getPromotedVTForPredicate()
21905 bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(  in SimplifyDemandedBitsForTargetNode()
21949 bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {  in isTargetCanonicalConstantNode()
21956 bool AArch64TargetLowering::isConstantUnsignedBitfieldExtractLegal(  in isConstantUnsignedBitfieldExtractLegal()