124     unsigned getOffsetReg() const {  in getOffsetReg()  function in __anon08bebcf20111::AArch64FastISel::Address
697     if (Addr.getOffsetReg())  in computeAddress()
770     if (Addr.getOffsetReg())  in computeAddress()
831     if (Addr.getOffsetReg())  in computeAddress()
861     if (!Addr.getReg() || Addr.getOffsetReg())  in computeAddress()
898   if (!Addr.getOffsetReg()) {  in computeAddress()
1025   if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.getOffsetReg())  in simplifyAddress()
1029   if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg())  in simplifyAddress()
1035   if ((ImmediateOffsetNeedsLowering || Addr.getOffsetReg()) && Addr.isFIBase())  in simplifyAddress()
1053                                   Addr.getOffsetReg(), Addr.getExtendType(),  in simplifyAddress()
1057                                   Addr.getOffsetReg(), AArch64_AM::LSL,  in simplifyAddress()
1061         ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),  in simplifyAddress()
1064         ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),  in simplifyAddress()
1067         ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),  in simplifyAddress()
1120       constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));  in addLoadStoreOperands()
1121     if (Addr.getOffsetReg()) {  in addLoadStoreOperands()
1126       MIB.addReg(Addr.getOffsetReg());  in addLoadStoreOperands()
1803                       Addr.getOffsetReg();  in emitLoad()
2093                       Addr.getOffsetReg();  in emitStore()