Lines Matching refs:emitIntExt
232 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1186 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2350 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*isZExt=*/true); in emitCompareAndBranch()
2856 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
3023 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
3033 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
3842 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
4049 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4152 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4190 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4233 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false); in emitASR_rr()
4268 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4322 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() function in AArch64FastISel
4523 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4885 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*isZExt=*/false); in getRegForGEPIndex()