157   MachineInstr *CmpMI;  member in __anoneb5605650111::SSACCmpConv
187   bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
383                                      const MachineInstr *CmpMI) {  in canSpeculateInstrs()  argument
427     if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {  in canSpeculateInstrs()
558   CmpMI = findConvertibleCompare(CmpBB);  in canConvert()
559   if (!CmpMI)  in canConvert()
562   if (!canSpeculateInstrs(CmpBB, CmpMI)) {  in canConvert()
654   switch (CmpMI->getOpcode()) {  in convert()
690   MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),  in convert()
692   if (CmpMI->getOperand(FirstOp + 1).isReg())  in convert()
693     MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),  in convert()
695   MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)  in convert()
696                                 .add(CmpMI->getOperand(FirstOp)); // Register Rn  in convert()
700     MIB.add(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate  in convert()
706     bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||  in convert()
707                 CmpMI->getOpcode() == AArch64::CBNZX;  in convert()
708     BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))  in convert()
710         .add(CmpMI->getOperand(1)); // Branch target.  in convert()
712   CmpMI->eraseFromParent();  in convert()
743   switch (CmpMI->getOpcode()) {  in expectedCodeSizeDelta()