Lines Matching refs:IntvOut
1622 unsigned IntvOut, SlotIndex EnterAfter){ in splitLiveThroughBlock() argument
1628 << ", live-through " << IntvIn << " -> " << IntvOut); in splitLiveThroughBlock()
1630 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks"); in splitLiveThroughBlock()
1638 if (!IntvOut) { in splitLiveThroughBlock()
1659 selectIntv(IntvOut); in splitLiveThroughBlock()
1666 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) { in splitLiveThroughBlock()
1672 selectIntv(IntvOut); in splitLiveThroughBlock()
1679 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf"); in splitLiveThroughBlock()
1681 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter || in splitLiveThroughBlock()
1689 selectIntv(IntvOut); in splitLiveThroughBlock()
1712 selectIntv(IntvOut); in splitLiveThroughBlock()
1817 unsigned IntvOut, SlotIndex EnterAfter) { in splitRegOutBlock() argument
1823 << BI.LastInstr << ", reg-out " << IntvOut in splitRegOutBlock()
1829 assert(IntvOut && "Must have register out"); in splitRegOutBlock()
1840 selectIntv(IntvOut); in splitRegOutBlock()
1852 selectIntv(IntvOut); in splitRegOutBlock()
1868 selectIntv(IntvOut); in splitRegOutBlock()