226     Topo.AddPredQueued(SU, D.getSUnit());  in AddPredQueued()
234     Topo.AddPred(SU, D.getSUnit());  in AddPred()
242     Topo.RemovePred(SU, D.getSUnit());  in RemovePred()
399   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()
564       assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) &&  in ReleasePredecessors()
566       LiveRegDefs[Pred.getReg()] = Pred.getSUnit();  in ReleasePredecessors()
821   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()
843       assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() &&  in UnscheduleNodeBottomUp()
899         LiveRegGens[Reg] = Succ.getSUnit();  in UnscheduleNodeBottomUp()
902               Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())  in UnscheduleNodeBottomUp()
903             LiveRegGens[Reg] = Succ2.getSUnit();  in UnscheduleNodeBottomUp()
1065     else if (isOperandOf(Pred.getSUnit(), LoadNode))  in TryUnfoldSU()
1093     SUnit *SuccDep = D.getSUnit();  in TryUnfoldSU()
1104     SUnit *SuccDep = D.getSUnit();  in TryUnfoldSU()
1201     SUnit *SuccSU = Succ.getSUnit();  in CopyAndMoveSuccessors()
1240     SUnit *SuccSU = Succ.getSUnit();  in InsertCopiesAndMoveSuccs()
1361       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs.get(),  in DelayForLiveRegsBottomUp()
1979       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
2002       SUnit *PredSU = Pred.getSUnit();  in CalcNodeSethiUllmanNumber()
2106     SUnit *PredSU = Pred.getSUnit();  in HighRegPressure()
2155     SUnit *PredSU = Pred.getSUnit();  in RegPressureDiff()
2198     SUnit *PredSU = Pred.getSUnit();  in scheduledNode()
2280     SUnit *PredSU = Pred.getSUnit();  in unscheduledNode()
2347     unsigned Height = Succ.getSUnit()->getHeight();  in closestSucc()
2350     if (Succ.getSUnit()->getNode() &&  in closestSucc()
2351         Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)  in closestSucc()
2352       Height = closestSucc(Succ.getSUnit())+1;  in closestSucc()
2376     const SUnit *PredSU = Pred.getSUnit();  in hasOnlyLiveInOpers()
2398     const SUnit *SuccSU = Succ.getSUnit();  in hasOnlyLiveOutUses()
2435     Pred.getSUnit()->isVRegCycle = true;  in initVRegCycle()
2447     SUnit *PredSU = Pred.getSUnit();  in resetVRegCycle()
2451       Pred.getSUnit()->isVRegCycle = false;  in resetVRegCycle()
2465     if (Pred.getSUnit()->isVRegCycle &&  in hasVRegCycleUse()
2466         Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasVRegCycleUse()
2864     SUnit *SuccSU = Succ.getSUnit();  in canClobberReachingPhysRegUse()
2871           scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))  in canClobberReachingPhysRegUse()
2880               scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))  in canClobberReachingPhysRegUse()
2977       if (Pred.isCtrl() && Pred.getSUnit()) {  in PrescheduleNodesWithMultipleUses()
2979         SDNode *PredND = Pred.getSUnit()->getNode();  in PrescheduleNodesWithMultipleUses()
3002         PredSU = Pred.getSUnit();  in PrescheduleNodesWithMultipleUses()
3024       SUnit *PredSuccSU = PredSucc.getSUnit();  in PrescheduleNodesWithMultipleUses()
3048       SUnit *SuccSU = Edge.getSUnit();  in PrescheduleNodesWithMultipleUses()
3095         SUnit *SuccSU = Succ.getSUnit();  in AddPseudoTwoAddrDeps()
3111           SuccSU = SuccSU->Succs.front().getSUnit();  in AddPseudoTwoAddrDeps()