Lines Matching refs:SUnit
150 std::vector<SUnit *> PendingQueue;
169 std::unique_ptr<SUnit*[]> LiveRegDefs;
170 std::unique_ptr<SUnit*[]> LiveRegGens;
174 SmallVector<SUnit*, 4> Interferences;
176 using LRegsMapT = DenseMap<SUnit *, SmallVector<unsigned, 4>>;
186 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable()
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle()
225 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued()
233 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
241 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
247 bool isReady(SUnit *SU) { in isReady()
252 void ReleasePred(SUnit *SU, const SDep *PredEdge);
253 void ReleasePredecessors(SUnit *SU);
256 void AdvancePastStalls(SUnit *SU);
257 void EmitNode(SUnit *SU);
258 void ScheduleNodeBottomUp(SUnit*);
260 void UnscheduleNodeBottomUp(SUnit*);
262 void BacktrackBottomUp(SUnit*, SUnit*);
263 SUnit *TryUnfoldSU(SUnit *);
264 SUnit *CopyAndMoveSuccessors(SUnit*);
265 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
268 SmallVectorImpl<SUnit*>&);
269 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
273 SUnit *PickNodeToScheduleBottomUp();
277 SUnit *CreateNewSUnit(SDNode *N) { in CreateNewSUnit()
279 SUnit *NewNode = newSUnit(N); in CreateNewSUnit()
287 SUnit *CreateClone(SUnit *N) { in CreateClone()
289 SUnit *NewNode = Clone(N); in CreateClone()
365 LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]()); in Schedule()
366 LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]()); in Schedule()
398 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
399 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
554 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { in ReleasePredecessors()
563 SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef; in ReleasePredecessors()
587 SUnit *Def = &SUnits[N->getNodeId()]; in ReleasePredecessors()
651 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) { in AdvancePastStalls()
693 void ScheduleDAGRRList::EmitNode(SUnit *SU) { in EmitNode()
731 static void resetVRegCycle(SUnit *SU);
736 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { in ScheduleNodeBottomUp()
821 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
835 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { in UnscheduleNodeBottomUp()
859 SUnit *SeqEnd = CallSeqEndForStart[SU]; in UnscheduleNodeBottomUp()
935 std::vector<SUnit *>::const_iterator I = (Sequence.end() - LookAhead); in RestoreHazardCheckerBottomUp()
938 SUnit *SU = *I; in RestoreHazardCheckerBottomUp()
948 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { in BacktrackBottomUp()
949 SUnit *OldSU = Sequence.back(); in BacktrackBottomUp()
970 static bool isOperandOf(const SUnit *SU, SDNode *N) { in isOperandOf()
980 SUnit *ScheduleDAGRRList::TryUnfoldSU(SUnit *SU) { in TryUnfoldSU()
1003 SUnit *LoadSU; in TryUnfoldSU()
1020 SUnit *NewSU; in TryUnfoldSU()
1093 SUnit *SuccDep = D.getSUnit(); in TryUnfoldSU()
1104 SUnit *SuccDep = D.getSUnit(); in TryUnfoldSU()
1134 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { in CopyAndMoveSuccessors()
1151 SUnit *NewSU; in CopyAndMoveSuccessors()
1173 SUnit *UnfoldSU = TryUnfoldSU(SU); in CopyAndMoveSuccessors()
1197 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in CopyAndMoveSuccessors()
1201 SUnit *SuccSU = Succ.getSUnit(); in CopyAndMoveSuccessors()
1222 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, in InsertCopiesAndMoveSuccs()
1225 SmallVectorImpl<SUnit*> &Copies) { in InsertCopiesAndMoveSuccs()
1226 SUnit *CopyFromSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1230 SUnit *CopyToSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1236 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in InsertCopiesAndMoveSuccs()
1240 SUnit *SuccSU = Succ.getSUnit(); in InsertCopiesAndMoveSuccs()
1297 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs, in CheckForLiveRegDef()
1323 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked()
1324 ArrayRef<SUnit*> LiveRegDefs, in CheckForLiveRegDefMasked()
1350 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) { in DelayForLiveRegsBottomUp()
1450 SUnit *SU = Interferences[i-1]; in releaseInterferences()
1476 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { in PickNodeToScheduleBottomUp()
1477 SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop(); in PickNodeToScheduleBottomUp()
1513 for (SUnit *TrySU : Interferences) { in PickNodeToScheduleBottomUp()
1518 SUnit *BtSU = nullptr; in PickNodeToScheduleBottomUp()
1564 SUnit *TrySU = Interferences[0]; in PickNodeToScheduleBottomUp()
1568 SUnit *LRDef = LiveRegDefs[Reg]; in PickNodeToScheduleBottomUp()
1581 SUnit *NewDef = nullptr; in PickNodeToScheduleBottomUp()
1589 SmallVector<SUnit*, 2> Copies; in PickNodeToScheduleBottomUp()
1616 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; in ListScheduleBottomUp()
1631 SUnit *SU = PickNodeToScheduleBottomUp(); in ListScheduleBottomUp()
1658 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } in isReady()
1668 bool operator()(SUnit* left, SUnit* right) const { in operator ()()
1688 bool operator()(SUnit* left, SUnit* right) const;
1702 bool operator()(SUnit* left, SUnit* right) const;
1716 bool isReady(SUnit *SU, unsigned CurCycle) const;
1718 bool operator()(SUnit* left, SUnit* right) const;
1733 bool isReady(SUnit *SU, unsigned CurCycle) const;
1735 bool operator()(SUnit* left, SUnit* right) const;
1740 std::vector<SUnit *> Queue;
1746 std::vector<SUnit> *SUnits;
1793 void initNodes(std::vector<SUnit> &sunits) override;
1795 void addNode(const SUnit *SU) override;
1797 void updateNode(const SUnit *SU) override;
1805 unsigned getNodePriority(const SUnit *SU) const;
1807 unsigned getNodeOrdering(const SUnit *SU) const { in getNodeOrdering()
1815 void push(SUnit *U) override { in push()
1821 void remove(SUnit *SU) override { in remove()
1824 std::vector<SUnit *>::iterator I = llvm::find(Queue, SU); in remove()
1835 bool HighRegPressure(const SUnit *SU) const;
1837 bool MayReduceRegPressure(SUnit *SU) const;
1839 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1841 void scheduledNode(SUnit *SU) override;
1843 void unscheduledNode(SUnit *SU) override;
1846 bool canClobber(const SUnit *SU, const SUnit *Op);
1853 static SUnit *popFromQueueImpl(std::vector<SUnit *> &Q, SF &Picker) { in popFromQueueImpl()
1861 SUnit *V = Q[BestIdx]; in popFromQueueImpl()
1869 SUnit *popFromQueue(std::vector<SUnit *> &Q, SF &Picker, ScheduleDAG *DAG) { in popFromQueue()
1904 bool isReady(SUnit *U) const override { in isReady()
1908 SUnit *pop() override { in pop()
1911 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG); in pop()
1919 std::vector<SUnit *> DumpQueue = Queue; in dump()
1922 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); in dump()
1947 static int checkSpecialNodes(const SUnit *left, const SUnit *right) { in checkSpecialNodes()
1958 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber()
1964 WorkState(const SUnit *SU) : SU(SU) {} in CalcNodeSethiUllmanNumber()
1965 const SUnit *SU; in CalcNodeSethiUllmanNumber()
1979 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
2002 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
2028 for (const SUnit &SU : *SUnits) in CalculateSethiUllmanNumbers()
2032 void RegReductionPQBase::addNode(const SUnit *SU) { in addNode()
2039 void RegReductionPQBase::updateNode(const SUnit *SU) { in updateNode()
2046 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { in getNodePriority()
2099 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { in HighRegPressure()
2106 SUnit *PredSU = Pred.getSUnit(); in HighRegPressure()
2124 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const { in MayReduceRegPressure()
2149 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { in RegPressureDiff()
2155 SUnit *PredSU = Pred.getSUnit(); in RegPressureDiff()
2188 void RegReductionPQBase::scheduledNode(SUnit *SU) { in scheduledNode()
2198 SUnit *PredSU = Pred.getSUnit(); in scheduledNode()
2257 void RegReductionPQBase::unscheduledNode(SUnit *SU) { in unscheduledNode()
2280 SUnit *PredSU = Pred.getSUnit(); in unscheduledNode()
2343 static unsigned closestSucc(const SUnit *SU) { in closestSucc()
2361 static unsigned calcMaxScratches(const SUnit *SU) { in calcMaxScratches()
2372 static bool hasOnlyLiveInOpers(const SUnit *SU) { in hasOnlyLiveInOpers()
2376 const SUnit *PredSU = Pred.getSUnit(); in hasOnlyLiveInOpers()
2394 static bool hasOnlyLiveOutUses(const SUnit *SU) { in hasOnlyLiveOutUses()
2398 const SUnit *SuccSU = Succ.getSUnit(); in hasOnlyLiveOutUses()
2422 static void initVRegCycle(SUnit *SU) { in initVRegCycle()
2441 static void resetVRegCycle(SUnit *SU) { in resetVRegCycle()
2447 SUnit *PredSU = Pred.getSUnit(); in resetVRegCycle()
2458 static bool hasVRegCycleUse(const SUnit *SU) { in hasVRegCycleUse()
2477 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) { in BUHasStall()
2487 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref, in BUCompareLatency()
2538 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) { in BURRSort()
2642 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2650 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2669 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2684 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2716 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2726 static bool canEnableCoalescing(SUnit *SU) { in canEnableCoalescing()
2750 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2811 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) { in initNodes()
2824 for (SUnit &SU : sunits) in initNodes()
2832 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { in canClobber()
2853 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, in canClobberReachingPhysRegUse()
2864 SUnit *SuccSU = Succ.getSUnit(); in canClobberReachingPhysRegUse()
2889 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, in canClobberPhysRegDefs()
2958 for (SUnit &SU : *SUnits) { in PrescheduleNodesWithMultipleUses()
2999 SUnit *PredSU = nullptr; in PrescheduleNodesWithMultipleUses()
3024 SUnit *PredSuccSU = PredSucc.getSUnit(); in PrescheduleNodesWithMultipleUses()
3048 SUnit *SuccSU = Edge.getSUnit(); in PrescheduleNodesWithMultipleUses()
3070 for (SUnit &SU : *SUnits) { in AddPseudoTwoAddrDeps()
3089 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; in AddPseudoTwoAddrDeps()
3095 SUnit *SuccSU = Succ.getSUnit(); in AddPseudoTwoAddrDeps()