1299                                SmallVectorImpl<unsigned> &LRegs,  in CheckForLiveRegDef()  argument
1316       LRegs.push_back(*AliasI);  in CheckForLiveRegDef()
1326                                      SmallVectorImpl<unsigned> &LRegs) {  in CheckForLiveRegDefMasked()  argument
1333       LRegs.push_back(i);  in CheckForLiveRegDefMasked()
1350 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {  in DelayForLiveRegsBottomUp()  argument
1362                          RegAdded, LRegs, TRI);  in DelayForLiveRegsBottomUp()
1386               CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);  in DelayForLiveRegsBottomUp()
1398         CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI,  in DelayForLiveRegsBottomUp()
1417           LRegs.push_back(CallResource);  in DelayForLiveRegsBottomUp()
1423                                RegAdded, LRegs);  in DelayForLiveRegsBottomUp()
1435           CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);  in DelayForLiveRegsBottomUp()
1441       CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);  in DelayForLiveRegsBottomUp()
1444   return !LRegs.empty();  in DelayForLiveRegsBottomUp()
1453       SmallVectorImpl<unsigned> &LRegs = LRegsPos->second;  in releaseInterferences()  local
1454       if (!is_contained(LRegs, Reg))  in releaseInterferences()
1480       SmallVector<unsigned, 4> LRegs;  in PickNodeToScheduleBottomUp()  local
1481       if (!DelayForLiveRegsBottomUp(CurSU, LRegs))  in PickNodeToScheduleBottomUp()
1484                  if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource";  in PickNodeToScheduleBottomUp()
1485                  else dbgs() << printReg(LRegs[0], TRI);  in PickNodeToScheduleBottomUp()
1488         LRegsMap.insert(std::make_pair(CurSU, LRegs));  in PickNodeToScheduleBottomUp()
1496         LRegsPair.first->second = LRegs;  in PickNodeToScheduleBottomUp()
1514     SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];  in PickNodeToScheduleBottomUp()  local
1520     for (unsigned Reg : LRegs) {  in PickNodeToScheduleBottomUp()
1565     SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];  in PickNodeToScheduleBottomUp()  local
1566     assert(LRegs.size() == 1 && "Can't handle this yet!");  in PickNodeToScheduleBottomUp()
1567     unsigned Reg = LRegs[0];  in PickNodeToScheduleBottomUp()