488   Register Op0 = getRegForValue(I->getOperand(0));  in selectBinaryOp()  local
489   if (!Op0) // Unhandled operand. Halt "fast" selection and bail.  in selectBinaryOp()
510     Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm,  in selectBinaryOp()
526                                    ISDOpcode, Op0, Op1);  in selectBinaryOp()
1418   Register Op0 = getRegForValue(I->getOperand(0));  in selectBitCast()  local
1419   if (!Op0) // Unhandled operand. Halt "fast" selection and bail.  in selectBitCast()
1424     updateValueMap(I, Op0);  in selectBitCast()
1429   Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0);  in selectBitCast()
1656   const Value *Op0 = EVI->getOperand(0);  in selectExtractValue()  local
1657   Type *AggTy = Op0->getType();  in selectExtractValue()
1661   DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(Op0);  in selectExtractValue()
1664   else if (isa<Instruction>(Op0))  in selectExtractValue()
1665     ResultReg = FuncInfo.InitializeRegForValue(Op0);  in selectExtractValue()
1861 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,  in fastEmit_ri_()  argument
1880   Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);  in fastEmit_ri_()
1893   return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);  in fastEmit_ri_()
1927                                   const TargetRegisterClass *RC, unsigned Op0) {  in fastEmitInst_r()  argument
1931   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());  in fastEmitInst_r()
1935         .addReg(Op0);  in fastEmitInst_r()
1938         .addReg(Op0);  in fastEmitInst_r()
1947                                    const TargetRegisterClass *RC, unsigned Op0,  in fastEmitInst_rr()  argument
1952   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());  in fastEmitInst_rr()
1957         .addReg(Op0)  in fastEmitInst_rr()
1961         .addReg(Op0)  in fastEmitInst_rr()
1970                                     const TargetRegisterClass *RC, unsigned Op0,  in fastEmitInst_rrr()  argument
1975   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());  in fastEmitInst_rrr()
1981         .addReg(Op0)  in fastEmitInst_rrr()
1986         .addReg(Op0)  in fastEmitInst_rrr()
1996                                    const TargetRegisterClass *RC, unsigned Op0,  in fastEmitInst_ri()  argument
2001   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());  in fastEmitInst_ri()
2005         .addReg(Op0)  in fastEmitInst_ri()
2009         .addReg(Op0)  in fastEmitInst_ri()
2018                                     const TargetRegisterClass *RC, unsigned Op0,  in fastEmitInst_rii()  argument
2023   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());  in fastEmitInst_rii()
2027         .addReg(Op0)  in fastEmitInst_rii()
2032         .addReg(Op0)  in fastEmitInst_rii()
2061                                     const TargetRegisterClass *RC, unsigned Op0,  in fastEmitInst_rri()  argument
2066   Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());  in fastEmitInst_rri()
2071         .addReg(Op0)  in fastEmitInst_rri()
2076         .addReg(Op0)  in fastEmitInst_rri()
2101 Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,  in fastEmitInst_extractsubreg()  argument
2104   assert(Register::isVirtualRegister(Op0) &&  in fastEmitInst_extractsubreg()
2106   const TargetRegisterClass *RC = MRI.getRegClass(Op0);  in fastEmitInst_extractsubreg()
2107   MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));  in fastEmitInst_extractsubreg()
2109           ResultReg).addReg(Op0, 0, Idx);  in fastEmitInst_extractsubreg()
2115 Register FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0) {  in fastEmitZExtFromI1()  argument
2116   return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);  in fastEmitZExtFromI1()