Lines Matching refs:SDep
252 SDep Dep; in addPhysRegDataDeps()
254 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
259 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
298 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
307 (Kind != SDep::Output || !MO.isDead() || in addPhysRegDeps()
309 SDep Dep(SU, Kind, /*Reg=*/*Alias); in addPhysRegDeps()
310 if (Kind != SDep::Anti) in addPhysRegDeps()
436 SDep Dep(SU, SDep::Data, Reg); in addVRegDefDeps()
479 SDep Dep(SU, SDep::Output, Reg); in addVRegDefDeps()
527 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg)); in addVRegUseDeps()
541 SDep Dep(SUa, SDep::MayAliasMem); in addChainDependency()
873 SDep Dep(SU, SDep::Artificial); in buildSchedGraph()
1195 bool ScheduleDAGInstrs::addEdge(SUnit *SuccSU, const SDep &PredDep) { in addEdge()
1274 for (const SDep &PredDep : SU->Preds) { in visitPostorderNode()
1275 if (PredDep.getKind() != SDep::Data) in visitPostorderNode()
1303 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) { in visitPostorderEdge()
1310 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) { in visitCrossEdge()
1353 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ, in joinPredSubtree()
1355 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges"); in joinPredSubtree()
1366 for (const SDep &SuccDep : PredSU->Succs) { in joinPredSubtree()
1367 if (SuccDep.getKind() == SDep::Data) { in joinPredSubtree()
1415 const SDep *backtrack() { in backtrack()
1432 for (const SDep &SuccDep : SU->Succs) { in hasDataSucc()
1433 if (SuccDep.getKind() == SDep::Data && in hasDataSucc()
1457 const SDep &PredDep = *DFS.getPred(); in compute()
1460 if (PredDep.getKind() != SDep::Data in compute()
1474 const SDep *PredDep = DFS.backtrack(); in compute()