229 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {  in addPhysRegDataDeps()  argument
230   const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);  in addPhysRegDataDeps()
239   bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() &&  in addPhysRegDataDeps()
268         Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,  in addPhysRegDataDeps()
273       ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);  in addPhysRegDataDeps()
282 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {  in addPhysRegDeps()  argument
284   MachineOperand &MO = MI->getOperand(OperIdx);  in addPhysRegDeps()
312             SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addPhysRegDeps()
313         ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep);  in addPhysRegDeps()
324     Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));  in addPhysRegDeps()
328     addPhysRegDataDeps(SU, OperIdx);  in addPhysRegDeps()
355     Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));  in addPhysRegDeps()
386 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {  in addVRegDefDeps()  argument
388   MachineOperand &MO = MI->getOperand(OperIdx);  in addVRegDefDeps()
406            llvm::drop_begin(MI->operands(), OperIdx + 1))  in addVRegDefDeps()
437         Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,  in addVRegDefDeps()
439         ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep);  in addVRegDefDeps()
481       SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addVRegDefDeps()
505 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {  in addVRegUseDeps()  argument
509   const MachineOperand &MO = MI->getOperand(OperIdx);  in addVRegUseDeps()
515   CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));  in addVRegUseDeps()