303       SUnit *DefSU = I->SU;  in addPhysRegDeps()  local
304       if (DefSU == &ExitSU)  in addPhysRegDeps()
306       if (DefSU != SU &&  in addPhysRegDeps()
308            !DefSU->getInstr()->registerDefIsDead(*Alias))) {  in addPhysRegDeps()
312             SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addPhysRegDeps()
313         ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep);  in addPhysRegDeps()
314         DefSU->addPred(Dep);  in addPhysRegDeps()
471     SUnit *DefSU = V2SU.SU;  in addVRegDefDeps()  local
477     if (DefSU == SU)  in addVRegDefDeps()
481       SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addVRegDefDeps()
482     DefSU->addPred(Dep);  in addVRegDefDeps()
492       CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));  in addVRegDefDeps()