Lines Matching refs:getOrCreateVReg
295 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateBinaryOp()
296 Register Op1 = getOrCreateVReg(*U.getOperand(1)); in translateBinaryOp()
297 Register Res = getOrCreateVReg(U); in translateBinaryOp()
310 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateUnaryOp()
311 Register Res = getOrCreateVReg(U); in translateUnaryOp()
328 Register Op0 = getOrCreateVReg(*U.getOperand(0)); in translateCompare()
329 Register Op1 = getOrCreateVReg(*U.getOperand(1)); in translateCompare()
330 Register Res = getOrCreateVReg(U); in translateCompare()
338 Res, getOrCreateVReg(*Constant::getNullValue(U.getType()))); in translateCompare()
341 Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType()))); in translateCompare()
780 Register SwitchOpReg = getOrCreateVReg(SValue); in emitJumpTableHeader()
801 auto Cst = getOrCreateVReg( in emitJumpTableHeader()
817 Register CondLHS = getOrCreateVReg(*CB.CmpLHS); in emitSwitchCase()
846 Register CondRHS = getOrCreateVReg(*CB.CmpRHS); in emitSwitchCase()
861 Register CmpOpReg = getOrCreateVReg(*CB.CmpMHS); in emitSwitchCase()
863 Register CondRHS = getOrCreateVReg(*CB.CmpRHS); in emitSwitchCase()
1005 Register SwitchOpReg = getOrCreateVReg(*B.SValue); in emitBitTestHeader()
1253 const Register Tgt = getOrCreateVReg(*BrInst.getAddress()); in translateIndirectBr()
1288 Register Base = getOrCreateVReg(*LI.getPointerOperand()); in translateLoad()
1342 Register Base = getOrCreateVReg(*SI.getPointerOperand()); in translateStore()
1435 Register Tst = getOrCreateVReg(*U.getOperand(0)); in translateSelect()
1453 Register Src = getOrCreateVReg(V); in translateCopy()
1478 Register Op = getOrCreateVReg(*U.getOperand(0)); in translateCast()
1479 Register Res = getOrCreateVReg(U); in translateCast()
1487 Register BaseReg = getOrCreateVReg(Op0); in translateGetElementPtr()
1544 Register IdxReg = getOrCreateVReg(*Idx); in translateGetElementPtr()
1573 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0)); in translateGetElementPtr()
1577 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
1593 Register SrcReg = getOrCreateVReg(**AI); in translateMemFunc()
1700 {getOrCreateVReg(*CI.getOperand(0)), getOrCreateVReg(*CI.getOperand(1))}); in translateOverflowIntrinsic()
1707 Register Dst = getOrCreateVReg(CI); in translateFixedPointIntrinsic()
1708 Register Src0 = getOrCreateVReg(*CI.getOperand(0)); in translateFixedPointIntrinsic()
1709 Register Src1 = getOrCreateVReg(*CI.getOperand(1)); in translateFixedPointIntrinsic()
1829 VRegs.push_back(getOrCreateVReg(*Arg)); in translateSimpleIntrinsic()
1831 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
1871 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(0))); in translateConstrainedFPIntrinsic()
1873 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(1))); in translateConstrainedFPIntrinsic()
1875 VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(2))); in translateConstrainedFPIntrinsic()
1877 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags); in translateConstrainedFPIntrinsic()
1952 MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), in translateKnownIntrinsic()
1978 MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)}) in translateKnownIntrinsic()
2062 Register Dst = getOrCreateVReg(CI); in translateKnownIntrinsic()
2063 Register Op0 = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2064 Register Op1 = getOrCreateVReg(*CI.getArgOperand(1)); in translateKnownIntrinsic()
2065 Register Op2 = getOrCreateVReg(*CI.getArgOperand(2)); in translateKnownIntrinsic()
2084 MIRBuilder.buildFPExt(getOrCreateVReg(CI), in translateKnownIntrinsic()
2085 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2090 MIRBuilder.buildFPTrunc(getOrCreateVReg(CI), in translateKnownIntrinsic()
2091 getOrCreateVReg(*CI.getArgOperand(0)), in translateKnownIntrinsic()
2104 Register Reg = getOrCreateVReg(CI); in translateKnownIntrinsic()
2116 getStackGuard(getOrCreateVReg(CI), MIRBuilder); in translateKnownIntrinsic()
2126 GuardVal = getOrCreateVReg(*CI.getArgOperand(0)); // The guard's value. in translateKnownIntrinsic()
2133 GuardVal, getOrCreateVReg(*Slot), in translateKnownIntrinsic()
2142 Register Reg = getOrCreateVReg(CI); in translateKnownIntrinsic()
2156 Register Reg = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2177 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2178 {getOrCreateVReg(*CI.getArgOperand(0))}); in translateKnownIntrinsic()
2195 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2196 getOrCreateVReg(*CI.getArgOperand(0))); in translateKnownIntrinsic()
2209 .buildInstr(TargetOpcode::G_READ_REGISTER, {getOrCreateVReg(CI)}, {}) in translateKnownIntrinsic()
2217 .addUse(getOrCreateVReg(*CI.getArgOperand(1))); in translateKnownIntrinsic()
2251 Register Dst = getOrCreateVReg(CI); in translateKnownIntrinsic()
2252 Register ScalarSrc = getOrCreateVReg(*CI.getArgOperand(0)); in translateKnownIntrinsic()
2253 Register VecSrc = getOrCreateVReg(*CI.getArgOperand(1)); in translateKnownIntrinsic()
2310 {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2311 {getOrCreateVReg(*CI.getArgOperand(0))}, Flags) in translateKnownIntrinsic()
2379 [&]() { return getOrCreateVReg(*CB.getCalledOperand()); }); in translateCallBase()
2701 Register Res = getOrCreateVReg(AI); in translateAlloca()
2712 Register NumElts = getOrCreateVReg(*AI.getArraySize()); in translateAlloca()
2725 getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, DL->getTypeAllocSize(Ty))); in translateAlloca()
2742 MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment); in translateAlloca()
2754 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)}, in translateVAArg()
2755 {getOrCreateVReg(*U.getOperand(0)), in translateVAArg()
2789 Register Res = getOrCreateVReg(U); in translateInsertElement()
2790 Register Val = getOrCreateVReg(*U.getOperand(0)); in translateInsertElement()
2791 Register Elt = getOrCreateVReg(*U.getOperand(1)); in translateInsertElement()
2792 Register Idx = getOrCreateVReg(*U.getOperand(2)); in translateInsertElement()
2804 Register Res = getOrCreateVReg(U); in translateExtractElement()
2805 Register Val = getOrCreateVReg(*U.getOperand(0)); in translateExtractElement()
2813 Idx = getOrCreateVReg(*NewIdxCI); in translateExtractElement()
2817 Idx = getOrCreateVReg(*U.getOperand(1)); in translateExtractElement()
2835 .buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)}, in translateShuffleVector()
2836 {getOrCreateVReg(*U.getOperand(0)), in translateShuffleVector()
2837 getOrCreateVReg(*U.getOperand(1))}) in translateShuffleVector()
2865 Register Addr = getOrCreateVReg(*I.getPointerOperand()); in translateAtomicCmpXchg()
2866 Register Cmp = getOrCreateVReg(*I.getCompareOperand()); in translateAtomicCmpXchg()
2867 Register NewVal = getOrCreateVReg(*I.getNewValOperand()); in translateAtomicCmpXchg()
2884 Register Res = getOrCreateVReg(I); in translateAtomicRMW()
2885 Register Addr = getOrCreateVReg(*I.getPointerOperand()); in translateAtomicRMW()
2886 Register Val = getOrCreateVReg(*I.getValOperand()); in translateAtomicRMW()
3047 Ops.push_back(getOrCreateVReg(Elt)); in translate()
3057 Ops.push_back(getOrCreateVReg(Elt)); in translate()
3074 Ops.push_back(getOrCreateVReg(*CV->getOperand(i))); in translate()
3275 Register GuardPtr = getOrCreateVReg(*IRGuard); in emitSPDescriptorParent()