Lines Matching refs:TargetOpcode
146 return isLegalOrBeforeLegalizer({TargetOpcode::G_CONSTANT, {Ty}}); in isConstantLegalOrBeforeLegalizer()
151 return isLegal({TargetOpcode::G_BUILD_VECTOR, {Ty, EltTy}}) && in isConstantLegalOrBeforeLegalizer()
152 isLegal({TargetOpcode::G_CONSTANT, {EltTy}}); in isConstantLegalOrBeforeLegalizer()
204 if (MI.getOpcode() != TargetOpcode::COPY) in matchCombineCopy()
229 assert(MI.getOpcode() == TargetOpcode::G_CONCAT_VECTORS && in matchCombineConcatVectors()
242 case TargetOpcode::G_BUILD_VECTOR: in matchCombineConcatVectors()
249 case TargetOpcode::G_IMPLICIT_DEF: { in matchCombineConcatVectors()
305 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR && in matchCombineShuffleVector()
404 CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
416 if (OpcodeForCandidate == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
417 CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
419 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
420 OpcodeForCandidate != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
426 if (CurrentUse.ExtendOpcode == TargetOpcode::G_SEXT && in ChoosePreferredUse()
427 OpcodeForCandidate == TargetOpcode::G_ZEXT) in ChoosePreferredUse()
429 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ZEXT && in ChoosePreferredUse()
430 OpcodeForCandidate == TargetOpcode::G_SEXT) in ChoosePreferredUse()
526 ? TargetOpcode::G_ANYEXT in matchCombineExtendingLoads()
527 : isa<GSExtLoad>(&MI) ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in matchCombineExtendingLoads()
530 if (UseMI.getOpcode() == TargetOpcode::G_SEXT || in matchCombineExtendingLoads()
531 UseMI.getOpcode() == TargetOpcode::G_ZEXT || in matchCombineExtendingLoads()
532 (UseMI.getOpcode() == TargetOpcode::G_ANYEXT)) { in matchCombineExtendingLoads()
535 if (MMO.isAtomic() && UseMI.getOpcode() != TargetOpcode::G_ANYEXT) in matchCombineExtendingLoads()
591 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT in applyCombineExtendingLoads()
592 ? TargetOpcode::G_SEXTLOAD in applyCombineExtendingLoads()
593 : Preferred.ExtendOpcode == TargetOpcode::G_ZEXT in applyCombineExtendingLoads()
594 ? TargetOpcode::G_ZEXTLOAD in applyCombineExtendingLoads()
595 : TargetOpcode::G_LOAD)); in applyCombineExtendingLoads()
609 UseMI->getOpcode() == TargetOpcode::G_ANYEXT) { in applyCombineExtendingLoads()
675 assert(MI.getOpcode() == TargetOpcode::G_AND); in matchCombineLoadWithAndMask()
740 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}})) in matchCombineLoadWithAndMask()
748 B.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, Dst, PtrReg, *NewMMO); in matchCombineLoadWithAndMask()
783 assert(MI.getOpcode() == TargetOpcode::G_SEXT_INREG); in matchSextTruncSextLoad()
809 assert(MI.getOpcode() == TargetOpcode::G_SEXT_INREG); in applySextTruncSextLoad()
817 assert(MI.getOpcode() == TargetOpcode::G_SEXT_INREG); in matchSextInRegOfLoad()
857 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_SEXTLOAD, in matchSextInRegOfLoad()
869 assert(MI.getOpcode() == TargetOpcode::G_SEXT_INREG); in applySextInRegOfLoad()
886 Builder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, MI.getOperand(0).getReg(), in applySextInRegOfLoad()
898 assert(Opcode == TargetOpcode::G_LOAD || Opcode == TargetOpcode::G_SEXTLOAD || in findPostIndexCandidate()
899 Opcode == TargetOpcode::G_ZEXTLOAD || Opcode == TargetOpcode::G_STORE); in findPostIndexCandidate()
904 if (BaseDef && BaseDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) in findPostIndexCandidate()
910 if (Use.getOpcode() != TargetOpcode::G_PTR_ADD) in findPostIndexCandidate()
966 assert(Opcode == TargetOpcode::G_LOAD || Opcode == TargetOpcode::G_SEXTLOAD || in findPreIndexCandidate()
967 Opcode == TargetOpcode::G_ZEXTLOAD || Opcode == TargetOpcode::G_STORE); in findPreIndexCandidate()
971 MachineInstr *AddrDef = getOpcodeDef(TargetOpcode::G_PTR_ADD, Addr, MRI); in findPreIndexCandidate()
987 if (BaseDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) { in findPreIndexCandidate()
992 if (MI.getOpcode() == TargetOpcode::G_STORE) { in findPreIndexCandidate()
1031 if (Opcode != TargetOpcode::G_LOAD && Opcode != TargetOpcode::G_SEXTLOAD && in matchCombineIndexedLoadStore()
1032 Opcode != TargetOpcode::G_ZEXTLOAD && Opcode != TargetOpcode::G_STORE) in matchCombineIndexedLoadStore()
1055 bool IsStore = Opcode == TargetOpcode::G_STORE; in applyCombineIndexedLoadStore()
1058 case TargetOpcode::G_LOAD: in applyCombineIndexedLoadStore()
1059 NewOpcode = TargetOpcode::G_INDEXED_LOAD; in applyCombineIndexedLoadStore()
1061 case TargetOpcode::G_SEXTLOAD: in applyCombineIndexedLoadStore()
1062 NewOpcode = TargetOpcode::G_INDEXED_SEXTLOAD; in applyCombineIndexedLoadStore()
1064 case TargetOpcode::G_ZEXTLOAD: in applyCombineIndexedLoadStore()
1065 NewOpcode = TargetOpcode::G_INDEXED_ZEXTLOAD; in applyCombineIndexedLoadStore()
1067 case TargetOpcode::G_STORE: in applyCombineIndexedLoadStore()
1068 NewOpcode = TargetOpcode::G_INDEXED_STORE; in applyCombineIndexedLoadStore()
1100 case TargetOpcode::G_SDIV: in matchCombineDivRem()
1101 case TargetOpcode::G_UDIV: { in matchCombineDivRem()
1103 IsSigned = Opcode == TargetOpcode::G_SDIV; in matchCombineDivRem()
1106 case TargetOpcode::G_SREM: in matchCombineDivRem()
1107 case TargetOpcode::G_UREM: { in matchCombineDivRem()
1109 IsSigned = Opcode == TargetOpcode::G_SREM; in matchCombineDivRem()
1117 DivOpcode = TargetOpcode::G_SDIV; in matchCombineDivRem()
1118 RemOpcode = TargetOpcode::G_SREM; in matchCombineDivRem()
1119 DivremOpcode = TargetOpcode::G_SDIVREM; in matchCombineDivRem()
1121 DivOpcode = TargetOpcode::G_UDIV; in matchCombineDivRem()
1122 RemOpcode = TargetOpcode::G_UREM; in matchCombineDivRem()
1123 DivremOpcode = TargetOpcode::G_UDIVREM; in matchCombineDivRem()
1161 if (Opcode == TargetOpcode::G_SDIV || Opcode == TargetOpcode::G_UDIV) { in applyCombineDivRem()
1170 Opcode == TargetOpcode::G_SDIV || Opcode == TargetOpcode::G_SREM; in applyCombineDivRem()
1179 Builder.buildInstr(IsSigned ? TargetOpcode::G_SDIVREM in applyCombineDivRem()
1180 : TargetOpcode::G_UDIVREM, in applyCombineDivRem()
1189 assert(MI.getOpcode() == TargetOpcode::G_BR); in matchOptBrCondByInvertingCond()
1211 if (BrCond->getOpcode() != TargetOpcode::G_BRCOND) in matchOptBrCondByInvertingCond()
1280 case TargetOpcode::G_FNEG: { in constantFoldFpUnary()
1284 case TargetOpcode::G_FABS: { in constantFoldFpUnary()
1288 case TargetOpcode::G_FPTRUNC: in constantFoldFpUnary()
1290 case TargetOpcode::G_FSQRT: { in constantFoldFpUnary()
1296 case TargetOpcode::G_FLOG2: { in constantFoldFpUnary()
1339 if (MI.getOpcode() != TargetOpcode::G_PTR_ADD) in matchPtrAddImmedChain()
1349 if (!Add2Def || Add2Def->getOpcode() != TargetOpcode::G_PTR_ADD) in matchPtrAddImmedChain()
1395 assert(MI.getOpcode() == TargetOpcode::G_PTR_ADD && "Expected G_PTR_ADD"); in applyPtrAddImmedChain()
1416 assert((Opcode == TargetOpcode::G_SHL || Opcode == TargetOpcode::G_ASHR || in matchShiftImmedChain()
1417 Opcode == TargetOpcode::G_LSHR || Opcode == TargetOpcode::G_SSHLSAT || in matchShiftImmedChain()
1418 Opcode == TargetOpcode::G_USHLSAT) && in matchShiftImmedChain()
1444 if (Opcode == TargetOpcode::G_USHLSAT && in matchShiftImmedChain()
1454 assert((Opcode == TargetOpcode::G_SHL || Opcode == TargetOpcode::G_ASHR || in applyShiftImmedChain()
1455 Opcode == TargetOpcode::G_LSHR || Opcode == TargetOpcode::G_SSHLSAT || in applyShiftImmedChain()
1456 Opcode == TargetOpcode::G_USHLSAT) && in applyShiftImmedChain()
1466 if (Opcode == TargetOpcode::G_SHL || Opcode == TargetOpcode::G_LSHR) { in applyShiftImmedChain()
1497 assert((ShiftOpcode == TargetOpcode::G_SHL || in matchShiftOfShiftedLogic()
1498 ShiftOpcode == TargetOpcode::G_ASHR || in matchShiftOfShiftedLogic()
1499 ShiftOpcode == TargetOpcode::G_LSHR || in matchShiftOfShiftedLogic()
1500 ShiftOpcode == TargetOpcode::G_USHLSAT || in matchShiftOfShiftedLogic()
1501 ShiftOpcode == TargetOpcode::G_SSHLSAT) && in matchShiftOfShiftedLogic()
1511 if (LogicOpcode != TargetOpcode::G_AND && LogicOpcode != TargetOpcode::G_OR && in matchShiftOfShiftedLogic()
1512 LogicOpcode != TargetOpcode::G_XOR) in matchShiftOfShiftedLogic()
1568 assert((Opcode == TargetOpcode::G_SHL || Opcode == TargetOpcode::G_ASHR || in applyShiftOfShiftedLogic()
1569 Opcode == TargetOpcode::G_LSHR || Opcode == TargetOpcode::G_USHLSAT || in applyShiftOfShiftedLogic()
1570 Opcode == TargetOpcode::G_SSHLSAT) && in applyShiftOfShiftedLogic()
1601 assert(MI.getOpcode() == TargetOpcode::G_MUL && "Expected a G_MUL"); in matchCombineMulToShl()
1613 assert(MI.getOpcode() == TargetOpcode::G_MUL && "Expected a G_MUL"); in applyCombineMulToShl()
1618 MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL)); in applyCombineMulToShl()
1626 assert(MI.getOpcode() == TargetOpcode::G_SHL && KB); in matchCombineShlOfExtend()
1649 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_SHL, {SrcTy, ShiftAmtTy}})) in matchCombineShlOfExtend()
1704 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && in matchCombineUnmergeMergeToPlainValues()
1728 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && in applyCombineUnmergeMergeToPlainValues()
1754 if (SrcInstr->getOpcode() != TargetOpcode::G_CONSTANT && in matchCombineUnmergeConstant()
1755 SrcInstr->getOpcode() != TargetOpcode::G_FCONSTANT) in matchCombineUnmergeConstant()
1759 APInt Val = SrcInstr->getOpcode() == TargetOpcode::G_CONSTANT in matchCombineUnmergeConstant()
1776 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && in applyCombineUnmergeConstant()
1805 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && in matchCombineUnmergeWithDeadLanesToTrunc()
1837 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && in matchCombineUnmergeZExtToZExt()
1863 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && in applyCombineUnmergeZExtToZExt()
1870 assert(ZExtInstr && ZExtInstr->getOpcode() == TargetOpcode::G_ZEXT && in applyCombineUnmergeZExtToZExt()
1899 assert((MI.getOpcode() == TargetOpcode::G_SHL || in matchCombineShiftToUnmerge()
1900 MI.getOpcode() == TargetOpcode::G_LSHR || in matchCombineShiftToUnmerge()
1901 MI.getOpcode() == TargetOpcode::G_ASHR) && "Expected a shift"); in matchCombineShiftToUnmerge()
1936 if (MI.getOpcode() == TargetOpcode::G_LSHR) { in applyCombineShiftToUnmerge()
1951 } else if (MI.getOpcode() == TargetOpcode::G_SHL) { in applyCombineShiftToUnmerge()
1965 assert(MI.getOpcode() == TargetOpcode::G_ASHR); in applyCombineShiftToUnmerge()
2006 assert(MI.getOpcode() == TargetOpcode::G_INTTOPTR && "Expected a G_INTTOPTR"); in matchCombineI2PToP2I()
2015 assert(MI.getOpcode() == TargetOpcode::G_INTTOPTR && "Expected a G_INTTOPTR"); in applyCombineI2PToP2I()
2023 assert(MI.getOpcode() == TargetOpcode::G_PTRTOINT && "Expected a G_PTRTOINT"); in matchCombineP2IToI2P()
2029 assert(MI.getOpcode() == TargetOpcode::G_PTRTOINT && "Expected a G_PTRTOINT"); in applyCombineP2IToI2P()
2038 assert(MI.getOpcode() == TargetOpcode::G_ADD); in matchCombineAddP2IToPtrAdd()
2112 assert(MI.getOpcode() == TargetOpcode::G_ANYEXT && "Expected a G_ANYEXT"); in matchCombineAnyExtTrunc()
2121 assert(MI.getOpcode() == TargetOpcode::G_ZEXT && "Expected a G_ZEXT"); in matchCombineZextTrunc()
2136 assert((MI.getOpcode() == TargetOpcode::G_ANYEXT || in matchCombineExtOfExt()
2137 MI.getOpcode() == TargetOpcode::G_SEXT || in matchCombineExtOfExt()
2138 MI.getOpcode() == TargetOpcode::G_ZEXT) && in matchCombineExtOfExt()
2146 (Opc == TargetOpcode::G_ANYEXT && in matchCombineExtOfExt()
2147 (SrcOpc == TargetOpcode::G_SEXT || SrcOpc == TargetOpcode::G_ZEXT)) || in matchCombineExtOfExt()
2148 (Opc == TargetOpcode::G_SEXT && SrcOpc == TargetOpcode::G_ZEXT)) { in matchCombineExtOfExt()
2157 assert((MI.getOpcode() == TargetOpcode::G_ANYEXT || in applyCombineExtOfExt()
2158 MI.getOpcode() == TargetOpcode::G_SEXT || in applyCombineExtOfExt()
2159 MI.getOpcode() == TargetOpcode::G_ZEXT) && in applyCombineExtOfExt()
2176 if (MI.getOpcode() == TargetOpcode::G_ANYEXT || in applyCombineExtOfExt()
2177 (MI.getOpcode() == TargetOpcode::G_SEXT && in applyCombineExtOfExt()
2178 SrcExtOp == TargetOpcode::G_ZEXT)) { in applyCombineExtOfExt()
2187 assert(MI.getOpcode() == TargetOpcode::G_MUL && "Expected a G_MUL"); in applyCombineMulByNegativeOne()
2199 assert(MI.getOpcode() == TargetOpcode::G_FNEG && "Expected a G_FNEG"); in matchCombineFNegOfFNeg()
2205 assert(MI.getOpcode() == TargetOpcode::G_FABS && "Expected a G_FABS"); in matchCombineFAbsOfFAbs()
2213 assert(MI.getOpcode() == TargetOpcode::G_FABS && "Expected a G_FABS"); in matchCombineFAbsOfFNeg()
2230 assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC"); in matchCombineTruncOfExt()
2234 if (SrcOpc == TargetOpcode::G_ANYEXT || SrcOpc == TargetOpcode::G_SEXT || in matchCombineTruncOfExt()
2235 SrcOpc == TargetOpcode::G_ZEXT) { in matchCombineTruncOfExt()
2244 assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC"); in applyCombineTruncOfExt()
2265 assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC"); in matchCombineTruncOfShl()
2275 {TargetOpcode::G_SHL, in matchCombineTruncOfShl()
2289 assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC"); in applyCombineTruncOfShl()
2306 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI); in matchAnyExplicitUseIsUndef()
2313 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI); in matchAllExplicitUsesAreUndef()
2318 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR); in matchUndefShuffleVectorMask()
2324 assert(MI.getOpcode() == TargetOpcode::G_STORE); in matchUndefStore()
2325 return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(), in matchUndefStore()
2330 assert(MI.getOpcode() == TargetOpcode::G_SELECT); in matchUndefSelectCmp()
2331 return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(), in matchUndefSelectCmp()
2478 assert(MI.getOpcode() == TargetOpcode::G_SELECT); in matchSelectSameVal()
2500 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI); in matchOperandIsUndef()
2563 assert(MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT && in matchCombineInsertVecElts()
2572 TargetOpcode::G_INSERT_VECTOR_ELT) in matchCombineInsertVecElts()
2589 if (CurrInst->getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) in matchCombineInsertVecElts()
2591 if (TmpInst->getOpcode() == TargetOpcode::G_BUILD_VECTOR) { in matchCombineInsertVecElts()
2599 return TmpInst->getOpcode() == TargetOpcode::G_IMPLICIT_DEF; in matchCombineInsertVecElts()
2639 assert(LogicOpcode == TargetOpcode::G_AND || in matchHoistLogicOpWithSameOpcodeHands()
2640 LogicOpcode == TargetOpcode::G_OR || in matchHoistLogicOpWithSameOpcodeHands()
2641 LogicOpcode == TargetOpcode::G_XOR); in matchHoistLogicOpWithSameOpcodeHands()
2679 case TargetOpcode::G_ANYEXT: in matchHoistLogicOpWithSameOpcodeHands()
2680 case TargetOpcode::G_SEXT: in matchHoistLogicOpWithSameOpcodeHands()
2681 case TargetOpcode::G_ZEXT: { in matchHoistLogicOpWithSameOpcodeHands()
2685 case TargetOpcode::G_AND: in matchHoistLogicOpWithSameOpcodeHands()
2686 case TargetOpcode::G_ASHR: in matchHoistLogicOpWithSameOpcodeHands()
2687 case TargetOpcode::G_LSHR: in matchHoistLogicOpWithSameOpcodeHands()
2688 case TargetOpcode::G_SHL: { in matchHoistLogicOpWithSameOpcodeHands()
2738 assert(MI.getOpcode() == TargetOpcode::G_ASHR); in matchAshrShlToSextInreg()
2748 {TargetOpcode::G_SEXT_INREG, {MRI.getType(Src)}})) in matchAshrShlToSextInreg()
2756 assert(MI.getOpcode() == TargetOpcode::G_ASHR); in applyAshShlToSextInreg()
2769 assert(MI.getOpcode() == TargetOpcode::G_AND); in matchOverlappingAnd()
2810 assert(MI.getOpcode() == TargetOpcode::G_AND); in matchRedundantAnd()
2856 assert(MI.getOpcode() == TargetOpcode::G_OR); in matchRedundantOr()
2911 assert(MI.getOpcode() == TargetOpcode::G_XOR); in matchNotCmp()
2941 case TargetOpcode::G_ICMP: in matchNotCmp()
2947 case TargetOpcode::G_FCMP: in matchNotCmp()
2953 case TargetOpcode::G_AND: in matchNotCmp()
2954 case TargetOpcode::G_OR: in matchNotCmp()
2996 case TargetOpcode::G_ICMP: in applyNotCmp()
2997 case TargetOpcode::G_FCMP: { in applyNotCmp()
3004 case TargetOpcode::G_AND: in applyNotCmp()
3005 Def->setDesc(Builder.getTII().get(TargetOpcode::G_OR)); in applyNotCmp()
3007 case TargetOpcode::G_OR: in applyNotCmp()
3008 Def->setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyNotCmp()
3021 assert(MI.getOpcode() == TargetOpcode::G_XOR); in matchXorOfAndWithSameReg()
3057 MI.setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyXorOfAndWithSameReg()
3115 if (Select->getOpcode() != TargetOpcode::G_SELECT || in matchFoldBinOpIntoSelect()
3120 if (Select->getOpcode() != TargetOpcode::G_SELECT || in matchFoldBinOpIntoSelect()
3143 (BinOpcode == TargetOpcode::G_AND || BinOpcode == TargetOpcode::G_OR) && in matchFoldBinOpIntoSelect()
3202 assert(Root->getOpcode() == TargetOpcode::G_OR && "Expected G_OR only!"); in findCandidatesForLoadOrCombine()
3246 if (const MachineInstr *Or = getOpcodeDef(TargetOpcode::G_OR, OrLHS, MRI)) in findCandidatesForLoadOrCombine()
3250 if (const MachineInstr *Or = getOpcodeDef(TargetOpcode::G_OR, OrRHS, MRI)) in findCandidatesForLoadOrCombine()
3434 assert(MI.getOpcode() == TargetOpcode::G_OR); in matchLoadOrCombine()
3494 if (NeedsBSwap && !isLegalOrBeforeLegalizer({TargetOpcode::G_BSWAP, {Ty}})) in matchLoadOrCombine()
3522 {TargetOpcode::G_LOAD, {Ty, MRI.getType(Ptr)}, {MMDesc}})) in matchLoadOrCombine()
3772 !isLegalOrBeforeLegalizer({TargetOpcode::G_BSWAP, {WideStoreTy}})) in matchTruncStoreMerge()
3775 !isLegalOrBeforeLegalizer({TargetOpcode::G_ROTR, {WideStoreTy}})) in matchTruncStoreMerge()
3815 assert(MI.getOpcode() == TargetOpcode::G_PHI); in matchExtendThroughPhis()
3829 case TargetOpcode::G_ANYEXT: in matchExtendThroughPhis()
3831 case TargetOpcode::G_ZEXT: in matchExtendThroughPhis()
3832 case TargetOpcode::G_SEXT: in matchExtendThroughPhis()
3849 case TargetOpcode::G_LOAD: in matchExtendThroughPhis()
3850 case TargetOpcode::G_TRUNC: in matchExtendThroughPhis()
3851 case TargetOpcode::G_SEXT: in matchExtendThroughPhis()
3852 case TargetOpcode::G_ZEXT: in matchExtendThroughPhis()
3853 case TargetOpcode::G_ANYEXT: in matchExtendThroughPhis()
3854 case TargetOpcode::G_CONSTANT: in matchExtendThroughPhis()
3870 assert(MI.getOpcode() == TargetOpcode::G_PHI); in applyExtendThroughPhis()
3899 auto NewPhi = Builder.buildInstrNoInsert(TargetOpcode::G_PHI); in applyExtendThroughPhis()
3915 assert(MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT); in matchExtractVecEltBuildVec()
3921 {TargetOpcode::G_BUILD_VECTOR, {SrcTy, SrcTy.getElementType()}})) in matchExtractVecEltBuildVec()
3930 getOpcodeDef(TargetOpcode::G_BUILD_VECTOR, SrcVec, MRI); in matchExtractVecEltBuildVec()
3932 BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR_TRUNC, SrcVec, MRI); in matchExtractVecEltBuildVec()
3937 {TargetOpcode::G_BUILD_VECTOR_TRUNC, {SrcTy, ScalarTy}})) in matchExtractVecEltBuildVec()
3971 assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR); in matchExtractAllEltsFromBuildVector()
3994 if (II.getOpcode() != TargetOpcode::G_EXTRACT_VECTOR_ELT) in matchExtractAllEltsFromBuildVector()
4013 assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR); in applyExtractAllEltsFromBuildVector()
4037 assert(MI.getOpcode() == TargetOpcode::G_OR); in matchOrShiftToFunnelShift()
4059 FshOpc = TargetOpcode::G_FSHR; in matchOrShiftToFunnelShift()
4066 FshOpc = TargetOpcode::G_FSHL; in matchOrShiftToFunnelShift()
4072 FshOpc = TargetOpcode::G_FSHR; in matchOrShiftToFunnelShift()
4091 assert(Opc == TargetOpcode::G_FSHL || Opc == TargetOpcode::G_FSHR); in matchFunnelShiftToRotate()
4097 Opc == TargetOpcode::G_FSHL ? TargetOpcode::G_ROTL : TargetOpcode::G_ROTR; in matchFunnelShiftToRotate()
4103 assert(Opc == TargetOpcode::G_FSHL || Opc == TargetOpcode::G_FSHR); in applyFunnelShiftToRotate()
4104 bool IsFSHL = Opc == TargetOpcode::G_FSHL; in applyFunnelShiftToRotate()
4106 MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL in applyFunnelShiftToRotate()
4107 : TargetOpcode::G_ROTR)); in applyFunnelShiftToRotate()
4114 assert(MI.getOpcode() == TargetOpcode::G_ROTL || in matchRotateOutOfRange()
4115 MI.getOpcode() == TargetOpcode::G_ROTR); in matchRotateOutOfRange()
4129 assert(MI.getOpcode() == TargetOpcode::G_ROTL || in applyRotateOutOfRange()
4130 MI.getOpcode() == TargetOpcode::G_ROTR); in applyRotateOutOfRange()
4145 assert(MI.getOpcode() == TargetOpcode::G_ICMP); in matchICmpToTrueFalseKnownBits()
4198 assert(MI.getOpcode() == TargetOpcode::G_ICMP); in matchICmpToLHSKnownBits()
4229 unsigned Op = TargetOpcode::COPY; in matchICmpToLHSKnownBits()
4231 Op = DstSize < LHSSize ? TargetOpcode::G_TRUNC : TargetOpcode::G_ZEXT; in matchICmpToLHSKnownBits()
4241 assert(MI.getOpcode() == TargetOpcode::G_AND); in matchAndOrDisjointMask()
4276 assert(MI.getOpcode() == TargetOpcode::G_SEXT_INREG); in matchBitfieldExtractFromSExtInReg()
4281 if (!LI || !LI->isLegalOrCustom({TargetOpcode::G_SBFX, {Ty, ExtractTy}})) in matchBitfieldExtractFromSExtInReg()
4305 assert(MI.getOpcode() == TargetOpcode::G_AND); in matchBitfieldExtractFromAnd()
4310 TargetOpcode::G_UBFX, Ty, ExtractTy)) in matchBitfieldExtractFromAnd()
4334 B.buildInstr(TargetOpcode::G_UBFX, {Dst}, {ShiftSrc, LSBCst, WidthCst}); in matchBitfieldExtractFromAnd()
4342 assert(Opcode == TargetOpcode::G_ASHR || Opcode == TargetOpcode::G_LSHR); in matchBitfieldExtractFromShr()
4346 const unsigned ExtrOpcode = Opcode == TargetOpcode::G_ASHR in matchBitfieldExtractFromShr()
4347 ? TargetOpcode::G_SBFX in matchBitfieldExtractFromShr()
4348 : TargetOpcode::G_UBFX; in matchBitfieldExtractFromShr()
4373 if (Opcode == TargetOpcode::G_ASHR && ShlAmt == ShrAmt) in matchBitfieldExtractFromShr()
4391 assert(Opcode == TargetOpcode::G_LSHR || Opcode == TargetOpcode::G_ASHR); in matchBitfieldExtractFromShrAnd()
4397 TargetOpcode::G_UBFX, Ty, ExtractTy)) in matchBitfieldExtractFromShrAnd()
4435 if (Opcode == TargetOpcode::G_ASHR && Width + ShrAmt == Size) in matchBitfieldExtractFromShrAnd()
4441 B.buildInstr(TargetOpcode::G_UBFX, {Dst}, {AndSrc, PosCst, WidthCst}); in matchBitfieldExtractFromShrAnd()
4448 assert(PtrAdd.getOpcode() == TargetOpcode::G_PTR_ADD); in reassociationCanBreakAddressingModePattern()
4451 MachineInstr *Src1Def = getOpcodeDef(TargetOpcode::G_PTR_ADD, Src1Reg, MRI); in reassociationCanBreakAddressingModePattern()
4476 while (ConvUseOpc == TargetOpcode::G_INTTOPTR || in reassociationCanBreakAddressingModePattern()
4477 ConvUseOpc == TargetOpcode::G_PTRTOINT) { in reassociationCanBreakAddressingModePattern()
4484 auto LoadStore = ConvUseOpc == TargetOpcode::G_LOAD || in reassociationCanBreakAddressingModePattern()
4485 ConvUseOpc == TargetOpcode::G_STORE; in reassociationCanBreakAddressingModePattern()
4519 if (RHS->getOpcode() != TargetOpcode::G_ADD) in matchReassocConstantInnerRHS()
4657 assert(MI.getOpcode() == TargetOpcode::G_AND); in matchNarrowBinopFeedingAnd()
4681 case TargetOpcode::G_ADD: in matchNarrowBinopFeedingAnd()
4682 case TargetOpcode::G_SUB: in matchNarrowBinopFeedingAnd()
4683 case TargetOpcode::G_MUL: in matchNarrowBinopFeedingAnd()
4684 case TargetOpcode::G_AND: in matchNarrowBinopFeedingAnd()
4685 case TargetOpcode::G_OR: in matchNarrowBinopFeedingAnd()
4686 case TargetOpcode::G_XOR: in matchNarrowBinopFeedingAnd()
4712 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {NarrowTy, WideTy}}) || in matchNarrowBinopFeedingAnd()
4713 !isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {WideTy, NarrowTy}})) in matchNarrowBinopFeedingAnd()
4732 assert(Opc == TargetOpcode::G_UMULO || Opc == TargetOpcode::G_SMULO); in matchMulOBy2()
4739 unsigned NewOpc = Opc == TargetOpcode::G_UMULO ? TargetOpcode::G_UADDO in matchMulOBy2()
4740 : TargetOpcode::G_SADDO; in matchMulOBy2()
4750 assert(MI.getOpcode() == TargetOpcode::G_UMULO || in matchMulOBy0()
4751 MI.getOpcode() == TargetOpcode::G_SMULO); in matchMulOBy0()
4768 assert(MI.getOpcode() == TargetOpcode::G_UADDO || in matchAddOBy0()
4769 MI.getOpcode() == TargetOpcode::G_SADDO); in matchAddOBy0()
4785 assert(MI.getOpcode() == TargetOpcode::G_UDIV); in buildUDivUsingMul()
4891 assert(MI.getOpcode() == TargetOpcode::G_UDIV); in matchUDivByConst()
4914 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_MUL, {DstTy, DstTy}})) in matchUDivByConst()
4916 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_UMULH, {DstTy}})) in matchUDivByConst()
4919 {TargetOpcode::G_ICMP, in matchUDivByConst()
4939 assert(MI.getOpcode() == TargetOpcode::G_UMULH); in matchUMulHToLShr()
4951 return isLegalOrBeforeLegalizer({TargetOpcode::G_LSHR, {Ty, ShiftAmtTy}}); in matchUMulHToLShr()
4974 assert(Opc == TargetOpcode::G_FADD || Opc == TargetOpcode::G_FSUB || in matchRedundantNegOperands()
4975 Opc == TargetOpcode::G_FMUL || Opc == TargetOpcode::G_FDIV || in matchRedundantNegOperands()
4976 Opc == TargetOpcode::G_FMAD || Opc == TargetOpcode::G_FMA); in matchRedundantNegOperands()
4987 isLegalOrBeforeLegalizer({TargetOpcode::G_FSUB, {Type}})) { in matchRedundantNegOperands()
4988 Opc = TargetOpcode::G_FSUB; in matchRedundantNegOperands()
4992 isLegalOrBeforeLegalizer({TargetOpcode::G_FADD, {Type}})) { in matchRedundantNegOperands()
4993 Opc = TargetOpcode::G_FADD; in matchRedundantNegOperands()
4999 else if ((Opc == TargetOpcode::G_FMUL || Opc == TargetOpcode::G_FDIV || in matchRedundantNegOperands()
5000 Opc == TargetOpcode::G_FMAD || Opc == TargetOpcode::G_FMA) && in matchRedundantNegOperands()
5020 if (MI.getOpcode() != TargetOpcode::G_FMUL) in isContractableFMul()
5051 isLegalOrBeforeLegalizer({TargetOpcode::G_FMA, {DstType}}); in canCombineFMadOrFMA()
5068 assert(MI.getOpcode() == TargetOpcode::G_FADD); in matchCombineFAddFMulToFMadOrFMA()
5079 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFAddFMulToFMadOrFMA()
5116 assert(MI.getOpcode() == TargetOpcode::G_FADD); in matchCombineFAddFpExtFMulToFMadOrFMA()
5130 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFAddFpExtFMulToFMadOrFMA()
5175 assert(MI.getOpcode() == TargetOpcode::G_FADD); in matchCombineFAddFMAFMulToFMadOrFMA()
5188 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFAddFMAFMulToFMadOrFMA()
5203 TargetOpcode::G_FMUL) && in matchCombineFAddFMAFMulToFMadOrFMA()
5212 TargetOpcode::G_FMUL) && in matchCombineFAddFMAFMulToFMadOrFMA()
5240 assert(MI.getOpcode() == TargetOpcode::G_FADD); in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5257 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFAddFpExtFMulToFMadOrFMAAggressive()
5366 assert(MI.getOpcode() == TargetOpcode::G_FSUB); in matchCombineFSubFMulToFMadOrFMA()
5387 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFSubFMulToFMadOrFMA()
5418 assert(MI.getOpcode() == TargetOpcode::G_FSUB); in matchCombineFSubFNegFMulToFMadOrFMA()
5429 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFSubFNegFMulToFMadOrFMA()
5465 assert(MI.getOpcode() == TargetOpcode::G_FSUB); in matchCombineFSubFpExtFMulToFMadOrFMA()
5476 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFSubFpExtFMulToFMadOrFMA()
5516 assert(MI.getOpcode() == TargetOpcode::G_FSUB); in matchCombineFSubFpExtFNegFMulToFMadOrFMA()
5528 HasFMAD ? TargetOpcode::G_FMAD : TargetOpcode::G_FMA; in matchCombineFSubFpExtFNegFMulToFMadOrFMA()
5635 case TargetOpcode::G_FMINNUM: in matchCombineFMinMaxNaN()
5636 case TargetOpcode::G_FMAXNUM: in matchCombineFMinMaxNaN()
5639 case TargetOpcode::G_FMINIMUM: in matchCombineFMinMaxNaN()
5640 case TargetOpcode::G_FMAXIMUM: in matchCombineFMinMaxNaN()
5658 assert(MI.getOpcode() == TargetOpcode::G_ADD && "Expected a G_ADD"); in matchAddSubSameReg()