Lines Matching refs:OpNum
85 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
166 unsigned OpNum = MI.getOperandNo(&MO); in isCrossCopy() local
167 DstSubIdx = MI.getOperand(OpNum+1).getImm(); in isCrossCopy()
226 unsigned OpNum = MI.getOperandNo(&MO); in transferUsedLanes() local
235 assert(OpNum % 2 == 1); in transferUsedLanes()
236 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes()
243 if (OpNum == 2) in transferUsedLanes()
255 assert(OpNum == 1); in transferUsedLanes()
259 assert(OpNum == 1); in transferUsedLanes()
289 unsigned OpNum = MI.getOperandNo(&Use); in transferDefinedLanesStep() local
292 DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes); in transferDefinedLanesStep()
305 unsigned OpNum, LaneBitmask DefinedLanes) const { in transferDefinedLanes() argument
310 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes()
317 if (OpNum == 2) { in transferDefinedLanes()
321 assert(OpNum == 1 && "INSERT_SUBREG must have two operands"); in transferDefinedLanes()
329 assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only"); in transferDefinedLanes()
398 unsigned OpNum = DefMI.getOperandNo(&MO); in determineInitialDefinedLanes() local
399 DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes); in determineInitialDefinedLanes()