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35 callable by device code, and *kernel functions*, which are callable by host
36 code. By default, the back-end will emit device functions. Metadata is used to
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46 function ``@my_kernel`` is callable from host code, but ``@my_fmad`` is not.
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66 When compiled, the PTX kernel functions are callable by host-side code.
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99 LLVM IR functions can read and write to this array, and host-side code can
111 The NVPTX target uses the module triple to select between 32/64-bit code
115 interface used by the generated code to communicate with the driver.  Most
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276 To accommodate various math-related compiler flags that can affect code
277 generation of libdevice code, the library code depends on a special LLVM IR
281 code often follows a pattern:
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313 often leave behind dead code of the form:
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323     ; Dead code
327 optimization pipeline before dead-code elimination.
330 of your pass manager; just use the following code when setting up your pass
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344 control code generation:
349 ``__CUDA_FTZ=[0,1]`` Use optimized code paths that flush subnormals to zero
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369 JIT compilation of PTX code to native GPU machine code.
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464 We can use the LLVM ``llc`` tool to directly run the NVPTX code generator:
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473   If you want to generate 32-bit code, change ``p:64:64:64`` to ``p:32:32:32``
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578 There is also a fifth address space used by the NVPTX code generator that
592 program), or a `device` function (callable only from GPU code). You can think
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625 execute our vector addition code is shown below. Note that for brevity this
626 code does not perform much error checking!
631   compile PTX to machine code (SASS) for a specific GPU architecture. Such
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