Lines Matching refs:start_value

16971       declare float @llvm.vector.reduce.fadd.v4f32(float %start_value, <4 x float> %a)
16972       declare double @llvm.vector.reduce.fadd.v2f64(double %start_value, <2 x double> %a)
16990     float sequential_fadd(start_value, input_vector)
16991       result = start_value
17012 …%ord = call float @llvm.vector.reduce.fadd.v4f32(float %start_value, <4 x float> %input) ; sequent…
17049       declare float @llvm.vector.reduce.fmul.v4f32(float %start_value, <4 x float> %a)
17050       declare double @llvm.vector.reduce.fmul.v2f64(double %start_value, <2 x double> %a)
17068     float sequential_fmul(start_value, input_vector)
17069       result = start_value
17090 …%ord = call float @llvm.vector.reduce.fmul.v4f32(float %start_value, <4 x float> %input) ; sequent…
19148 …declare i32 @llvm.vp.reduce.add.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <ve…
19149 …declare i16 @llvm.vp.reduce.add.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x…
19172 ``val`` on each enabled lane, adding it to the scalar ``start_value``. Disabled
19175 to ``start_value``.
19204 …declare float @llvm.vp.reduce.fadd.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, …
19205 …declare double @llvm.vp.reduce.fadd.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vs…
19230 ``start_value``. Disabled lanes are treated as containing the neutral value
19232 enabled, the resulting value will be equal to ``start_value``.
19263 …declare i32 @llvm.vp.reduce.mul.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <ve…
19264 …declare i16 @llvm.vp.reduce.mul.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x…
19288 on each enabled lane, multiplying it by the scalar ``start_value``. Disabled
19319 …declare float @llvm.vp.reduce.fmul.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, …
19320 …declare double @llvm.vp.reduce.fmul.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vs…
19346 `start_value``. Disabled lanes are treated as containing the neutral value
19379 …declare i32 @llvm.vp.reduce.and.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <ve…
19380 …declare i16 @llvm.vp.reduce.and.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x…
19405 scalar ``start_value``. Disabled lanes are treated as containing the neutral
19436 …declare i32 @llvm.vp.reduce.or.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <vec…
19437 …declare i16 @llvm.vp.reduce.or.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x …
19462 ``start_value``. Disabled lanes are treated as containing the neutral value
19492 …declare i32 @llvm.vp.reduce.xor.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <ve…
19493 …declare i16 @llvm.vp.reduce.xor.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 x…
19518 ``start_value``. Disabled lanes are treated as containing the neutral value
19549 …declare i32 @llvm.vp.reduce.smax.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <v…
19550 …declare i16 @llvm.vp.reduce.smax.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 …
19575 the scalar ``start_value``. Disabled lanes are treated as containing the
19606 …declare i32 @llvm.vp.reduce.smin.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <v…
19607 …declare i16 @llvm.vp.reduce.smin.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 …
19632 the scalar ``start_value``. Disabled lanes are treated as containing the
19663 …declare i32 @llvm.vp.reduce.umax.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <v…
19664 …declare i16 @llvm.vp.reduce.umax.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 …
19689 the scalar ``start_value``. Disabled lanes are treated as containing the
19720 …declare i32 @llvm.vp.reduce.umin.v4i32(i32 <start_value>, <4 x i32> <val>, <4 x i1> <mask>, i32 <v…
19721 …declare i16 @llvm.vp.reduce.umin.nxv8i16(i16 <start_value>, <vscale x 8 x i16> <val>, <vscale x 8 …
19746 scalar ``start_value``. Disabled lanes are treated as containing the neutral
19777 …declare float @llvm.vp.reduce.fmax.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, …
19778 …declare double @llvm.vp.reduce.fmax.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vs…
19804 scalar ``start_value``. Disabled lanes are treated as containing the neutral
19847 …declare float @llvm.vp.reduce.fmin.v4f32(float <start_value>, <4 x float> <val>, <4 x i1> <mask>, …
19848 …declare double @llvm.vp.reduce.fmin.nxv8f64(double <start_value>, <vscale x 8 x double> <val>, <vs…
19874 scalar ``start_value``. Disabled lanes are treated as containing the neutral