Lines Matching refs:may

32 A sequence of *vector* registers may be used to operate with more than 32 bits of data.
45                                                         *N* may be specified as an
50                                                         *N* and *K* may be specified as
85 GFX10 *Image* instructions may use special *NSA* (Non-Sequential Address) syntax for *image address…
91                                           Each register may be specified using syntax
97                                           may appear in the list more than once.
115 A sequence of *accumulator* registers may be used to operate with more than 32 bits of data.
128 …                                                                         *N* may be specified as an
133 …                                                                    *N* and *K* may be specified as
187 A sequence of *scalar* registers may be used to operate with more than 32 bits of data.
203                                                              *N* may be specified as an
208                                                              *N* and *K* may be specified as
275 A sequence of *ttmp* registers may be used to operate with more than 32 bits of data.
290                                                                   *N* may be specified as an
295                                                                   *N* and *K* may be specified as
348 High and low 32 bits of *trap base address* may be accessed as separate registers:
377 High and low 32 bits of *trap memory address* may be accessed as separate registers:
406 High and low 32 bits of *flat scratch* address may be accessed as separate registers:
442 High and low 32 bits of *xnack mask* may be accessed as separate registers:
476 High and low 32 bits of *vector condition code* may be accessed as separate registers:
521 High and low 32 bits of *execute mask* may be accessed as separate registers:
570 This is a special operand which may be used as a source or a destination.
594 If a number may be encoded as either
608 Only a small fraction of integer numbers may be encoded as *inline constants*.
629 Only a small fraction of floating-point numbers may be encoded as *inline constants*.
681 If a number may be encoded as either
686 Literals may be specified as :ref:`integer numbers<amdgpu_synid_integer_number>`,
691 An instruction may use only one literal but several operands may refer the same literal.
759 Integer numbers may be specified in binary, octal, hexadecimal and decimal formats:
781 Floating-point numbers may be specified in hexadecimal and decimal formats:
858 Expressions may also use "." which is a reference to the current PC (program counter).
970 A symbol may be used before it is declared or assigned;
973 Additional information about symbols may be found :ref:`here<amdgpu-symbols>`.
991 Instruction operands may be specified as 64-bit :ref:`integer numbers<amdgpu_synid_integer_number>`…
995 1. *Validation*. Assembler checks if the input value may be truncated without loss to the required …
1058 Instruction operands may be specified as 64-bit :ref:`floating-point numbers<amdgpu_synid_floating-…
1081 …                                          Note that the result may differ from the original number.
1119 may be used with 32-bit integer operands and jump targets.