409 #define EXPECT_GPR_MIPS64(lldb_reg, fbsd_regno)                                \  macro
426   EXPECT_GPR_MIPS64(zero, 0);  in TEST()
427   EXPECT_GPR_MIPS64(r1, 1);  in TEST()
428   EXPECT_GPR_MIPS64(r2, 2);  in TEST()
429   EXPECT_GPR_MIPS64(r3, 3);  in TEST()
430   EXPECT_GPR_MIPS64(r4, 4);  in TEST()
431   EXPECT_GPR_MIPS64(r5, 5);  in TEST()
432   EXPECT_GPR_MIPS64(r6, 6);  in TEST()
433   EXPECT_GPR_MIPS64(r7, 7);  in TEST()
434   EXPECT_GPR_MIPS64(r8, 8);  in TEST()
435   EXPECT_GPR_MIPS64(r9, 9);  in TEST()
436   EXPECT_GPR_MIPS64(r10, 10);  in TEST()
437   EXPECT_GPR_MIPS64(r11, 11);  in TEST()
438   EXPECT_GPR_MIPS64(r12, 12);  in TEST()
439   EXPECT_GPR_MIPS64(r13, 13);  in TEST()
440   EXPECT_GPR_MIPS64(r14, 14);  in TEST()
441   EXPECT_GPR_MIPS64(r15, 15);  in TEST()
442   EXPECT_GPR_MIPS64(r16, 16);  in TEST()
443   EXPECT_GPR_MIPS64(r17, 17);  in TEST()
444   EXPECT_GPR_MIPS64(r18, 18);  in TEST()
445   EXPECT_GPR_MIPS64(r19, 19);  in TEST()
446   EXPECT_GPR_MIPS64(r20, 20);  in TEST()
447   EXPECT_GPR_MIPS64(r21, 21);  in TEST()
448   EXPECT_GPR_MIPS64(r22, 22);  in TEST()
449   EXPECT_GPR_MIPS64(r23, 23);  in TEST()
450   EXPECT_GPR_MIPS64(r24, 24);  in TEST()
451   EXPECT_GPR_MIPS64(r25, 25);  in TEST()
452   EXPECT_GPR_MIPS64(r26, 26);  in TEST()
453   EXPECT_GPR_MIPS64(r27, 27);  in TEST()
454   EXPECT_GPR_MIPS64(gp, 28);  in TEST()
455   EXPECT_GPR_MIPS64(sp, 29);  in TEST()
456   EXPECT_GPR_MIPS64(r30, 30);  in TEST()
457   EXPECT_GPR_MIPS64(ra, 31);  in TEST()
458   EXPECT_GPR_MIPS64(sr, 32);  in TEST()
459   EXPECT_GPR_MIPS64(mullo, 33);  in TEST()
460   EXPECT_GPR_MIPS64(mulhi, 34);  in TEST()
461   EXPECT_GPR_MIPS64(badvaddr, 35);  in TEST()
462   EXPECT_GPR_MIPS64(cause, 36);  in TEST()
463   EXPECT_GPR_MIPS64(pc, 37);  in TEST()
464   EXPECT_GPR_MIPS64(ic, 38);  in TEST()
465   EXPECT_GPR_MIPS64(dummy, 39);  in TEST()