Lines Matching refs:fpu
272 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1; in GetFPUState()
273 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1; in GetFPUState()
274 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234; in GetFPUState()
275 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678; in GetFPUState()
276 m_state.context.fpu.no_avx.__fpu_ftw = 1; in GetFPUState()
277 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX; in GetFPUState()
278 m_state.context.fpu.no_avx.__fpu_fop = 2; in GetFPUState()
279 m_state.context.fpu.no_avx.__fpu_ip = 3; in GetFPUState()
280 m_state.context.fpu.no_avx.__fpu_cs = 4; in GetFPUState()
281 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5; in GetFPUState()
282 m_state.context.fpu.no_avx.__fpu_dp = 6; in GetFPUState()
283 m_state.context.fpu.no_avx.__fpu_ds = 7; in GetFPUState()
284 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX; in GetFPUState()
285 m_state.context.fpu.no_avx.__fpu_mxcsr = 8; in GetFPUState()
286 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9; in GetFPUState()
289 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a'; in GetFPUState()
290 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b'; in GetFPUState()
291 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c'; in GetFPUState()
292 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd'; in GetFPUState()
293 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e'; in GetFPUState()
294 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f'; in GetFPUState()
295 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g'; in GetFPUState()
296 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h'; in GetFPUState()
298 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; in GetFPUState()
299 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; in GetFPUState()
300 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; in GetFPUState()
301 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; in GetFPUState()
302 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; in GetFPUState()
303 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; in GetFPUState()
304 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; in GetFPUState()
305 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; in GetFPUState()
308 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0'; in GetFPUState()
309 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1'; in GetFPUState()
310 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2'; in GetFPUState()
311 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3'; in GetFPUState()
312 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4'; in GetFPUState()
313 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5'; in GetFPUState()
314 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6'; in GetFPUState()
315 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7'; in GetFPUState()
316 m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8'; in GetFPUState()
317 m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9'; in GetFPUState()
318 m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A'; in GetFPUState()
319 m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B'; in GetFPUState()
320 m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C'; in GetFPUState()
321 m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D'; in GetFPUState()
322 m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E'; in GetFPUState()
323 m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F'; in GetFPUState()
325 for (int i = 0; i < sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i) in GetFPUState()
326 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN; in GetFPUState()
327 m_state.context.fpu.no_avx.__fpu_reserved1 = -1; in GetFPUState()
331 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0' + i; in GetFPUState()
332 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1' + i; in GetFPUState()
333 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2' + i; in GetFPUState()
334 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3' + i; in GetFPUState()
335 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4' + i; in GetFPUState()
336 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5' + i; in GetFPUState()
337 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6' + i; in GetFPUState()
338 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7' + i; in GetFPUState()
339 m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8' + i; in GetFPUState()
340 m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9' + i; in GetFPUState()
341 m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A' + i; in GetFPUState()
342 m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B' + i; in GetFPUState()
343 m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C' + i; in GetFPUState()
344 m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D' + i; in GetFPUState()
345 m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E' + i; in GetFPUState()
346 m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F' + i; in GetFPUState()
348 for (int i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i) in GetFPUState()
349 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN; in GetFPUState()
353 m_state.context.fpu.avx512f.__fpu_k0.__opmask_reg[i] = '0'; in GetFPUState()
354 m_state.context.fpu.avx512f.__fpu_k1.__opmask_reg[i] = '1'; in GetFPUState()
355 m_state.context.fpu.avx512f.__fpu_k2.__opmask_reg[i] = '2'; in GetFPUState()
356 m_state.context.fpu.avx512f.__fpu_k3.__opmask_reg[i] = '3'; in GetFPUState()
357 m_state.context.fpu.avx512f.__fpu_k4.__opmask_reg[i] = '4'; in GetFPUState()
358 m_state.context.fpu.avx512f.__fpu_k5.__opmask_reg[i] = '5'; in GetFPUState()
359 m_state.context.fpu.avx512f.__fpu_k6.__opmask_reg[i] = '6'; in GetFPUState()
360 m_state.context.fpu.avx512f.__fpu_k7.__opmask_reg[i] = '7'; in GetFPUState()
364 m_state.context.fpu.avx512f.__fpu_zmmh0.__ymm_reg[i] = '0'; in GetFPUState()
365 m_state.context.fpu.avx512f.__fpu_zmmh1.__ymm_reg[i] = '1'; in GetFPUState()
366 m_state.context.fpu.avx512f.__fpu_zmmh2.__ymm_reg[i] = '2'; in GetFPUState()
367 m_state.context.fpu.avx512f.__fpu_zmmh3.__ymm_reg[i] = '3'; in GetFPUState()
368 m_state.context.fpu.avx512f.__fpu_zmmh4.__ymm_reg[i] = '4'; in GetFPUState()
369 m_state.context.fpu.avx512f.__fpu_zmmh5.__ymm_reg[i] = '5'; in GetFPUState()
370 m_state.context.fpu.avx512f.__fpu_zmmh6.__ymm_reg[i] = '6'; in GetFPUState()
371 m_state.context.fpu.avx512f.__fpu_zmmh7.__ymm_reg[i] = '7'; in GetFPUState()
372 m_state.context.fpu.avx512f.__fpu_zmmh8.__ymm_reg[i] = '8'; in GetFPUState()
373 m_state.context.fpu.avx512f.__fpu_zmmh9.__ymm_reg[i] = '9'; in GetFPUState()
374 m_state.context.fpu.avx512f.__fpu_zmmh10.__ymm_reg[i] = 'A'; in GetFPUState()
375 m_state.context.fpu.avx512f.__fpu_zmmh11.__ymm_reg[i] = 'B'; in GetFPUState()
376 m_state.context.fpu.avx512f.__fpu_zmmh12.__ymm_reg[i] = 'C'; in GetFPUState()
377 m_state.context.fpu.avx512f.__fpu_zmmh13.__ymm_reg[i] = 'D'; in GetFPUState()
378 m_state.context.fpu.avx512f.__fpu_zmmh14.__ymm_reg[i] = 'E'; in GetFPUState()
379 m_state.context.fpu.avx512f.__fpu_zmmh15.__ymm_reg[i] = 'F'; in GetFPUState()
382 m_state.context.fpu.avx512f.__fpu_zmm16.__zmm_reg[i] = 'G'; in GetFPUState()
383 m_state.context.fpu.avx512f.__fpu_zmm17.__zmm_reg[i] = 'H'; in GetFPUState()
384 m_state.context.fpu.avx512f.__fpu_zmm18.__zmm_reg[i] = 'I'; in GetFPUState()
385 m_state.context.fpu.avx512f.__fpu_zmm19.__zmm_reg[i] = 'J'; in GetFPUState()
386 m_state.context.fpu.avx512f.__fpu_zmm20.__zmm_reg[i] = 'K'; in GetFPUState()
387 m_state.context.fpu.avx512f.__fpu_zmm21.__zmm_reg[i] = 'L'; in GetFPUState()
388 m_state.context.fpu.avx512f.__fpu_zmm22.__zmm_reg[i] = 'M'; in GetFPUState()
389 m_state.context.fpu.avx512f.__fpu_zmm23.__zmm_reg[i] = 'N'; in GetFPUState()
390 m_state.context.fpu.avx512f.__fpu_zmm24.__zmm_reg[i] = 'O'; in GetFPUState()
391 m_state.context.fpu.avx512f.__fpu_zmm25.__zmm_reg[i] = 'P'; in GetFPUState()
392 m_state.context.fpu.avx512f.__fpu_zmm26.__zmm_reg[i] = 'Q'; in GetFPUState()
393 m_state.context.fpu.avx512f.__fpu_zmm27.__zmm_reg[i] = 'R'; in GetFPUState()
394 m_state.context.fpu.avx512f.__fpu_zmm28.__zmm_reg[i] = 'S'; in GetFPUState()
395 m_state.context.fpu.avx512f.__fpu_zmm29.__zmm_reg[i] = 'T'; in GetFPUState()
396 m_state.context.fpu.avx512f.__fpu_zmm30.__zmm_reg[i] = 'U'; in GetFPUState()
397 m_state.context.fpu.avx512f.__fpu_zmm31.__zmm_reg[i] = 'V'; in GetFPUState()
414 (thread_state_t)&m_state.context.fpu, in GetFPUState()
433 (thread_state_t)&m_state.context.fpu, in GetFPUState()
504 (thread_state_t)&m_state.context.fpu, count)); in SetFPUState()
519 (thread_state_t)&m_state.context.fpu, count)); in SetFPUState()
1551 offsetof(DNBArchImplX86_64::Context, fpu.no_avx))
1554 offsetof(DNBArchImplX86_64::Context, fpu.avx))
1557 offsetof(DNBArchImplX86_64::Context, fpu.avx512f))
2331 *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); in GetRegisterValue()
2335 *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); in GetRegisterValue()
2338 memcpy (&value->value.uint16, &m_state.context.fpu.no_avx.__fpu_ftw, 2); in GetRegisterValue()
2341 value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; in GetRegisterValue()
2344 value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; in GetRegisterValue()
2347 value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; in GetRegisterValue()
2350 value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; in GetRegisterValue()
2353 value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; in GetRegisterValue()
2356 value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; in GetRegisterValue()
2359 value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; in GetRegisterValue()
2371 &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); in GetRegisterValue()
2391 &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); in GetRegisterValue()
2411 &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16); in GetRegisterValue()
2413 &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16); in GetRegisterValue()
2424 &m_state.context.fpu.avx512f.__fpu_k0 + (reg - fpu_k0), 8); in GetRegisterValue()
2443 &m_state.context.fpu.avx512f.__fpu_xmm0 + (reg - fpu_zmm0), 16); in GetRegisterValue()
2445 &m_state.context.fpu.avx512f.__fpu_ymmh0 + (reg - fpu_zmm0), 16); in GetRegisterValue()
2447 &m_state.context.fpu.avx512f.__fpu_zmmh0 + (reg - fpu_zmm0), 32); in GetRegisterValue()
2466 &m_state.context.fpu.avx512f.__fpu_zmm16 + (reg - fpu_zmm16), 64); in GetRegisterValue()
2539 *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = in SetRegisterValue()
2544 *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = in SetRegisterValue()
2549 memcpy (&m_state.context.fpu.no_avx.__fpu_ftw, &value->value.uint8, 2); in SetRegisterValue()
2553 m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; in SetRegisterValue()
2557 m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; in SetRegisterValue()
2561 m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; in SetRegisterValue()
2565 m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; in SetRegisterValue()
2569 m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; in SetRegisterValue()
2573 m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; in SetRegisterValue()
2577 m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; in SetRegisterValue()
2589 memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), in SetRegisterValue()
2610 memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), in SetRegisterValue()
2631 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), in SetRegisterValue()
2633 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), in SetRegisterValue()
2645 memcpy(&m_state.context.fpu.avx512f.__fpu_k0 + (reg - fpu_k0), in SetRegisterValue()
2665 memcpy(&m_state.context.fpu.avx512f.__fpu_xmm0 + (reg - fpu_zmm0), in SetRegisterValue()
2667 memcpy(&m_state.context.fpu.avx512f.__fpu_ymmh0 + (reg - fpu_zmm0), in SetRegisterValue()
2669 memcpy(&m_state.context.fpu.avx512f.__fpu_zmmh0 + (reg - fpu_zmm0), in SetRegisterValue()
2689 memcpy(&m_state.context.fpu.avx512f.__fpu_zmm16 + (reg - fpu_zmm16), in SetRegisterValue()
2784 memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5); in GetRegisterContext()
2788 memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8); in GetRegisterContext()
2790 memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6); in GetRegisterContext()
2792 memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8); in GetRegisterContext()
2798 memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10); in GetRegisterContext()
2804 memcpy(p, &m_state.context.fpu.avx512f.__fpu_k0 + i, 8); in GetRegisterContext()
2812 memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16); in GetRegisterContext()
2814 memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16); in GetRegisterContext()
2819 memcpy(p, &m_state.context.fpu.avx512f.__fpu_zmmh0 + i, 32); in GetRegisterContext()
2823 memcpy(p, &m_state.context.fpu.avx512f.__fpu_zmm16 + i, 64); in GetRegisterContext()
2829 memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 16 * 16); in GetRegisterContext()
2868 memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5); in SetRegisterContext()
2872 memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8); in SetRegisterContext()
2874 memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6); in SetRegisterContext()
2876 memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8); in SetRegisterContext()
2882 memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10); in SetRegisterContext()
2888 memcpy(&m_state.context.fpu.avx512f.__fpu_k0 + i, p, 8); in SetRegisterContext()
2896 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16); in SetRegisterContext()
2898 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16); in SetRegisterContext()
2903 memcpy(&m_state.context.fpu.avx512f.__fpu_zmmh0 + i, p, 32); in SetRegisterContext()
2907 memcpy(&m_state.context.fpu.avx512f.__fpu_zmm16 + i, p, 64); in SetRegisterContext()
2913 memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 16 * 16); in SetRegisterContext()
2979 m_state.context.fpu = pos->second.fpu; in RestoreRegisterState()