Lines Matching refs:NULL
64 int error = ::sysctlbyname(feature, &answer, &answer_size, NULL, 0); in DetectHardwareFeature()
96 int err = ::sysctl(mib, 2, &buffer, &length, NULL, 0); in CPUHasAVX()
108 auto major_ver = strtoull(buffer, NULL, 0); in CPUHasAVX()
1564 #define GPR_SIZE(reg) (sizeof(((DNBArchImplX86_64::GPR *)NULL)->__##reg))
1566 (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg))
1568 (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__mmst_reg))
1570 (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg))
1573 #define EXC_SIZE(reg) (sizeof(((DNBArchImplX86_64::EXC *)NULL)->__##reg))
1581 e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, GPR_SIZE(reg), \
1583 INVALID_NUB_REGNUM, debugserver_##reg, NULL, g_invalidate_##reg \
1589 debugserver_##reg, NULL, g_invalidate_##reg \
1595 INVALID_NUB_REGNUM, debugserver_##reg, NULL, NULL \
1601 debugserver_##reg, NULL, NULL \
1607 debugserver_##reg, NULL, NULL \
1612 e_regSetGPR, gpr_##reg32, #reg32, NULL, Uint, Hex, 4, 0, \
1618 e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, 0, \
1624 e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 1, INVALID_NUB_REGNUM, \
1630 e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 0, INVALID_NUB_REGNUM, \
1637 const char *g_contained_rax[] = {"rax", NULL};
1638 const char *g_contained_rbx[] = {"rbx", NULL};
1639 const char *g_contained_rcx[] = {"rcx", NULL};
1640 const char *g_contained_rdx[] = {"rdx", NULL};
1641 const char *g_contained_rdi[] = {"rdi", NULL};
1642 const char *g_contained_rsi[] = {"rsi", NULL};
1643 const char *g_contained_rbp[] = {"rbp", NULL};
1644 const char *g_contained_rsp[] = {"rsp", NULL};
1645 const char *g_contained_r8[] = {"r8", NULL};
1646 const char *g_contained_r9[] = {"r9", NULL};
1647 const char *g_contained_r10[] = {"r10", NULL};
1648 const char *g_contained_r11[] = {"r11", NULL};
1649 const char *g_contained_r12[] = {"r12", NULL};
1650 const char *g_contained_r13[] = {"r13", NULL};
1651 const char *g_contained_r14[] = {"r14", NULL};
1652 const char *g_contained_r15[] = {"r15", NULL};
1654 const char *g_invalidate_rax[] = {"rax", "eax", "ax", "ah", "al", NULL};
1655 const char *g_invalidate_rbx[] = {"rbx", "ebx", "bx", "bh", "bl", NULL};
1656 const char *g_invalidate_rcx[] = {"rcx", "ecx", "cx", "ch", "cl", NULL};
1657 const char *g_invalidate_rdx[] = {"rdx", "edx", "dx", "dh", "dl", NULL};
1658 const char *g_invalidate_rdi[] = {"rdi", "edi", "di", "dil", NULL};
1659 const char *g_invalidate_rsi[] = {"rsi", "esi", "si", "sil", NULL};
1660 const char *g_invalidate_rbp[] = {"rbp", "ebp", "bp", "bpl", NULL};
1661 const char *g_invalidate_rsp[] = {"rsp", "esp", "sp", "spl", NULL};
1662 const char *g_invalidate_r8[] = {"r8", "r8d", "r8w", "r8l", NULL};
1663 const char *g_invalidate_r9[] = {"r9", "r9d", "r9w", "r9l", NULL};
1664 const char *g_invalidate_r10[] = {"r10", "r10d", "r10w", "r10l", NULL};
1665 const char *g_invalidate_r11[] = {"r11", "r11d", "r11w", "r11l", NULL};
1666 const char *g_invalidate_r12[] = {"r12", "r12d", "r12w", "r12l", NULL};
1667 const char *g_invalidate_r13[] = {"r13", "r13d", "r13w", "r13l", NULL};
1668 const char *g_invalidate_r14[] = {"r14", "r14d", "r14w", "r14l", NULL};
1669 const char *g_invalidate_r15[] = {"r15", "r15d", "r15w", "r15l", NULL};
1690 DEFINE_GPR_ALT2(cs, NULL),
1691 DEFINE_GPR_ALT2(fs, NULL),
1692 DEFINE_GPR_ALT2(gs, NULL),
1748 {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
1749 FPU_OFFSET(fcw), -1U, -1U, -1U, -1U, NULL, NULL},
1750 {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
1751 FPU_OFFSET(fsw), -1U, -1U, -1U, -1U, NULL, NULL},
1752 {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
1753 FPU_OFFSET(ftw), -1U, -1U, -1U, -1U, NULL, NULL},
1754 {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
1755 FPU_OFFSET(fop), -1U, -1U, -1U, -1U, NULL, NULL},
1756 {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
1757 FPU_OFFSET(ip), -1U, -1U, -1U, -1U, NULL, NULL},
1758 {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
1759 FPU_OFFSET(cs), -1U, -1U, -1U, -1U, NULL, NULL},
1760 {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
1761 FPU_OFFSET(dp), -1U, -1U, -1U, -1U, NULL, NULL},
1762 {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
1763 FPU_OFFSET(ds), -1U, -1U, -1U, -1U, NULL, NULL},
1764 {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
1765 FPU_OFFSET(mxcsr), -1U, -1U, -1U, -1U, NULL, NULL},
1766 {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
1767 FPU_SIZE_UINT(mxcsrmask), FPU_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
1768 NULL},
1772 ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
1775 ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
1778 ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
1781 ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
1784 ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
1787 ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
1790 ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
1793 ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
1795 {e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8,
1797 ehframe_dwarf_xmm0, -1U, debugserver_xmm0, NULL, NULL},
1798 {e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8,
1800 ehframe_dwarf_xmm1, -1U, debugserver_xmm1, NULL, NULL},
1801 {e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8,
1803 ehframe_dwarf_xmm2, -1U, debugserver_xmm2, NULL, NULL},
1804 {e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8,
1806 ehframe_dwarf_xmm3, -1U, debugserver_xmm3, NULL, NULL},
1807 {e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8,
1809 ehframe_dwarf_xmm4, -1U, debugserver_xmm4, NULL, NULL},
1810 {e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8,
1812 ehframe_dwarf_xmm5, -1U, debugserver_xmm5, NULL, NULL},
1813 {e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8,
1815 ehframe_dwarf_xmm6, -1U, debugserver_xmm6, NULL, NULL},
1816 {e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8,
1818 ehframe_dwarf_xmm7, -1U, debugserver_xmm7, NULL, NULL},
1819 {e_regSetFPU, fpu_xmm8, "xmm8", NULL, Vector, VectorOfUInt8,
1821 ehframe_dwarf_xmm8, -1U, debugserver_xmm8, NULL, NULL},
1822 {e_regSetFPU, fpu_xmm9, "xmm9", NULL, Vector, VectorOfUInt8,
1824 ehframe_dwarf_xmm9, -1U, debugserver_xmm9, NULL, NULL},
1825 {e_regSetFPU, fpu_xmm10, "xmm10", NULL, Vector, VectorOfUInt8,
1827 ehframe_dwarf_xmm10, -1U, debugserver_xmm10, NULL, NULL},
1828 {e_regSetFPU, fpu_xmm11, "xmm11", NULL, Vector, VectorOfUInt8,
1830 ehframe_dwarf_xmm11, -1U, debugserver_xmm11, NULL, NULL},
1831 {e_regSetFPU, fpu_xmm12, "xmm12", NULL, Vector, VectorOfUInt8,
1833 ehframe_dwarf_xmm12, -1U, debugserver_xmm12, NULL, NULL},
1834 {e_regSetFPU, fpu_xmm13, "xmm13", NULL, Vector, VectorOfUInt8,
1836 ehframe_dwarf_xmm13, -1U, debugserver_xmm13, NULL, NULL},
1837 {e_regSetFPU, fpu_xmm14, "xmm14", NULL, Vector, VectorOfUInt8,
1839 ehframe_dwarf_xmm14, -1U, debugserver_xmm14, NULL, NULL},
1840 {e_regSetFPU, fpu_xmm15, "xmm15", NULL, Vector, VectorOfUInt8,
1842 ehframe_dwarf_xmm15, -1U, debugserver_xmm15, NULL, NULL},
1845 static const char *g_contained_ymm0[] = {"ymm0", NULL};
1846 static const char *g_contained_ymm1[] = {"ymm1", NULL};
1847 static const char *g_contained_ymm2[] = {"ymm2", NULL};
1848 static const char *g_contained_ymm3[] = {"ymm3", NULL};
1849 static const char *g_contained_ymm4[] = {"ymm4", NULL};
1850 static const char *g_contained_ymm5[] = {"ymm5", NULL};
1851 static const char *g_contained_ymm6[] = {"ymm6", NULL};
1852 static const char *g_contained_ymm7[] = {"ymm7", NULL};
1853 static const char *g_contained_ymm8[] = {"ymm8", NULL};
1854 static const char *g_contained_ymm9[] = {"ymm9", NULL};
1855 static const char *g_contained_ymm10[] = {"ymm10", NULL};
1856 static const char *g_contained_ymm11[] = {"ymm11", NULL};
1857 static const char *g_contained_ymm12[] = {"ymm12", NULL};
1858 static const char *g_contained_ymm13[] = {"ymm13", NULL};
1859 static const char *g_contained_ymm14[] = {"ymm14", NULL};
1860 static const char *g_contained_ymm15[] = {"ymm15", NULL};
1863 {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
1864 AVX_OFFSET(fcw), -1U, -1U, -1U, -1U, NULL, NULL},
1865 {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
1866 AVX_OFFSET(fsw), -1U, -1U, -1U, -1U, NULL, NULL},
1867 {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
1868 AVX_OFFSET(ftw), -1U, -1U, -1U, -1U, NULL, NULL},
1869 {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
1870 AVX_OFFSET(fop), -1U, -1U, -1U, -1U, NULL, NULL},
1871 {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
1872 AVX_OFFSET(ip), -1U, -1U, -1U, -1U, NULL, NULL},
1873 {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
1874 AVX_OFFSET(cs), -1U, -1U, -1U, -1U, NULL, NULL},
1875 {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
1876 AVX_OFFSET(dp), -1U, -1U, -1U, -1U, NULL, NULL},
1877 {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
1878 AVX_OFFSET(ds), -1U, -1U, -1U, -1U, NULL, NULL},
1879 {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
1880 AVX_OFFSET(mxcsr), -1U, -1U, -1U, -1U, NULL, NULL},
1881 {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
1882 FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
1883 NULL},
1887 ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
1890 ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
1893 ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
1896 ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
1899 ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
1902 ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
1905 ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
1908 ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
1910 {e_regSetFPU, fpu_ymm0, "ymm0", NULL, Vector, VectorOfUInt8,
1912 ehframe_dwarf_ymm0, -1U, debugserver_ymm0, NULL, NULL},
1913 {e_regSetFPU, fpu_ymm1, "ymm1", NULL, Vector, VectorOfUInt8,
1915 ehframe_dwarf_ymm1, -1U, debugserver_ymm1, NULL, NULL},
1916 {e_regSetFPU, fpu_ymm2, "ymm2", NULL, Vector, VectorOfUInt8,
1918 ehframe_dwarf_ymm2, -1U, debugserver_ymm2, NULL, NULL},
1919 {e_regSetFPU, fpu_ymm3, "ymm3", NULL, Vector, VectorOfUInt8,
1921 ehframe_dwarf_ymm3, -1U, debugserver_ymm3, NULL, NULL},
1922 {e_regSetFPU, fpu_ymm4, "ymm4", NULL, Vector, VectorOfUInt8,
1924 ehframe_dwarf_ymm4, -1U, debugserver_ymm4, NULL, NULL},
1925 {e_regSetFPU, fpu_ymm5, "ymm5", NULL, Vector, VectorOfUInt8,
1927 ehframe_dwarf_ymm5, -1U, debugserver_ymm5, NULL, NULL},
1928 {e_regSetFPU, fpu_ymm6, "ymm6", NULL, Vector, VectorOfUInt8,
1930 ehframe_dwarf_ymm6, -1U, debugserver_ymm6, NULL, NULL},
1931 {e_regSetFPU, fpu_ymm7, "ymm7", NULL, Vector, VectorOfUInt8,
1933 ehframe_dwarf_ymm7, -1U, debugserver_ymm7, NULL, NULL},
1934 {e_regSetFPU, fpu_ymm8, "ymm8", NULL, Vector, VectorOfUInt8,
1936 ehframe_dwarf_ymm8, -1U, debugserver_ymm8, NULL, NULL},
1937 {e_regSetFPU, fpu_ymm9, "ymm9", NULL, Vector, VectorOfUInt8,
1939 ehframe_dwarf_ymm9, -1U, debugserver_ymm9, NULL, NULL},
1940 {e_regSetFPU, fpu_ymm10, "ymm10", NULL, Vector, VectorOfUInt8,
1942 ehframe_dwarf_ymm10, -1U, debugserver_ymm10, NULL, NULL},
1943 {e_regSetFPU, fpu_ymm11, "ymm11", NULL, Vector, VectorOfUInt8,
1945 ehframe_dwarf_ymm11, -1U, debugserver_ymm11, NULL, NULL},
1946 {e_regSetFPU, fpu_ymm12, "ymm12", NULL, Vector, VectorOfUInt8,
1948 ehframe_dwarf_ymm12, -1U, debugserver_ymm12, NULL, NULL},
1949 {e_regSetFPU, fpu_ymm13, "ymm13", NULL, Vector, VectorOfUInt8,
1951 ehframe_dwarf_ymm13, -1U, debugserver_ymm13, NULL, NULL},
1952 {e_regSetFPU, fpu_ymm14, "ymm14", NULL, Vector, VectorOfUInt8,
1954 ehframe_dwarf_ymm14, -1U, debugserver_ymm14, NULL, NULL},
1955 {e_regSetFPU, fpu_ymm15, "ymm15", NULL, Vector, VectorOfUInt8,
1957 ehframe_dwarf_ymm15, -1U, debugserver_ymm15, NULL, NULL},
1959 {e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8,
1961 debugserver_xmm0, g_contained_ymm0, NULL},
1962 {e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8,
1964 debugserver_xmm1, g_contained_ymm1, NULL},
1965 {e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8,
1967 debugserver_xmm2, g_contained_ymm2, NULL},
1968 {e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8,
1970 debugserver_xmm3, g_contained_ymm3, NULL},
1971 {e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8,
1973 debugserver_xmm4, g_contained_ymm4, NULL},
1974 {e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8,
1976 debugserver_xmm5, g_contained_ymm5, NULL},
1977 {e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8,
1979 debugserver_xmm6, g_contained_ymm6, NULL},
1980 {e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8,
1982 debugserver_xmm7, g_contained_ymm7, NULL},
1983 {e_regSetFPU, fpu_xmm8, "xmm8", NULL, Vector, VectorOfUInt8,
1985 debugserver_xmm8, g_contained_ymm8, NULL},
1986 {e_regSetFPU, fpu_xmm9, "xmm9", NULL, Vector, VectorOfUInt8,
1988 debugserver_xmm9, g_contained_ymm9, NULL},
1989 {e_regSetFPU, fpu_xmm10, "xmm10", NULL, Vector, VectorOfUInt8,
1991 debugserver_xmm10, g_contained_ymm10, NULL},
1992 {e_regSetFPU, fpu_xmm11, "xmm11", NULL, Vector, VectorOfUInt8,
1994 debugserver_xmm11, g_contained_ymm11, NULL},
1995 {e_regSetFPU, fpu_xmm12, "xmm12", NULL, Vector, VectorOfUInt8,
1997 debugserver_xmm12, g_contained_ymm12, NULL},
1998 {e_regSetFPU, fpu_xmm13, "xmm13", NULL, Vector, VectorOfUInt8,
2000 debugserver_xmm13, g_contained_ymm13, NULL},
2001 {e_regSetFPU, fpu_xmm14, "xmm14", NULL, Vector, VectorOfUInt8,
2003 debugserver_xmm14, g_contained_ymm14, NULL},
2004 {e_regSetFPU, fpu_xmm15, "xmm15", NULL, Vector, VectorOfUInt8,
2006 debugserver_xmm15, g_contained_ymm15, NULL}
2010 static const char *g_contained_zmm0[] = {"zmm0", NULL};
2011 static const char *g_contained_zmm1[] = {"zmm1", NULL};
2012 static const char *g_contained_zmm2[] = {"zmm2", NULL};
2013 static const char *g_contained_zmm3[] = {"zmm3", NULL};
2014 static const char *g_contained_zmm4[] = {"zmm4", NULL};
2015 static const char *g_contained_zmm5[] = {"zmm5", NULL};
2016 static const char *g_contained_zmm6[] = {"zmm6", NULL};
2017 static const char *g_contained_zmm7[] = {"zmm7", NULL};
2018 static const char *g_contained_zmm8[] = {"zmm8", NULL};
2019 static const char *g_contained_zmm9[] = {"zmm9", NULL};
2020 static const char *g_contained_zmm10[] = {"zmm10", NULL};
2021 static const char *g_contained_zmm11[] = {"zmm11", NULL};
2022 static const char *g_contained_zmm12[] = {"zmm12", NULL};
2023 static const char *g_contained_zmm13[] = {"zmm13", NULL};
2024 static const char *g_contained_zmm14[] = {"zmm14", NULL};
2025 static const char *g_contained_zmm15[] = {"zmm15", NULL};
2031 e_regSetFPU, fpu_zmm##reg, STR(zmm##reg), NULL, Vector, VectorOfUInt8, \
2034 debugserver_zmm##reg, NULL, NULL \
2039 e_regSetFPU, fpu_ymm##reg, STR(ymm##reg), NULL, Vector, VectorOfUInt8, \
2042 g_contained_zmm##reg, NULL \
2047 e_regSetFPU, fpu_xmm##reg, STR(xmm##reg), NULL, Vector, VectorOfUInt8, \
2050 g_contained_zmm##reg, NULL \
2055 e_regSetFPU, fpu_k##reg, STR(k##reg), NULL, Vector, VectorOfUInt8, 8, \
2057 -1U, debugserver_k##reg, NULL, NULL \
2061 {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
2062 AVX_OFFSET(fcw), -1U, -1U, -1U, -1U, NULL, NULL},
2063 {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
2064 AVX_OFFSET(fsw), -1U, -1U, -1U, -1U, NULL, NULL},
2065 {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
2066 AVX_OFFSET(ftw), -1U, -1U, -1U, -1U, NULL, NULL},
2067 {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
2068 AVX_OFFSET(fop), -1U, -1U, -1U, -1U, NULL, NULL},
2069 {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
2070 AVX_OFFSET(ip), -1U, -1U, -1U, -1U, NULL, NULL},
2071 {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
2072 AVX_OFFSET(cs), -1U, -1U, -1U, -1U, NULL, NULL},
2073 {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
2074 AVX_OFFSET(dp), -1U, -1U, -1U, -1U, NULL, NULL},
2075 {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
2076 AVX_OFFSET(ds), -1U, -1U, -1U, -1U, NULL, NULL},
2077 {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
2078 AVX_OFFSET(mxcsr), -1U, -1U, -1U, -1U, NULL, NULL},
2079 {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
2080 FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
2081 NULL},
2085 ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
2088 ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
2091 ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
2094 ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
2097 ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
2100 ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
2103 ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
2106 ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
2190 {e_regSetEXC, exc_trapno, "trapno", NULL, Uint, Hex, EXC_SIZE(trapno),
2191 EXC_OFFSET(trapno), -1U, -1U, -1U, -1U, NULL, NULL},
2192 {e_regSetEXC, exc_err, "err", NULL, Uint, Hex, EXC_SIZE(err),
2193 EXC_OFFSET(err), -1U, -1U, -1U, -1U, NULL, NULL},
2194 {e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex,
2195 EXC_SIZE(faultvaddr), EXC_OFFSET(faultvaddr), -1U, -1U, -1U, -1U, NULL,
2196 NULL}};
2220 {"x86_64 Registers", NULL, k_num_all_registers_no_avx},
2227 {"x86_64 Registers", NULL, k_num_all_registers_avx},
2233 {"x86_64 Registers", NULL, k_num_all_registers_avx},
2253 return NULL; in SoftwareBreakpointOpcode()
2725 if (g_fpu_registers_avx512f[i].value_regs == NULL) in GetRegisterContextSize()
2730 if (g_fpu_registers_avx[i].value_regs == NULL) in GetRegisterContextSize()
2735 if (g_fpu_registers_no_avx[i].value_regs == NULL) in GetRegisterContextSize()
2855 if (buf == NULL || buf_len == 0) in SetRegisterContext()