Lines Matching refs:m_state
327 return m_state.context.gpr.__eip; in GetPC()
335 m_state.context.gpr.__eip = static_cast<uint32_t>(value); in SetPC()
344 return m_state.context.gpr.__esp; in GetSP()
353 if (force || m_state.GetError(e_regSetGPR, Read)) { in GetGPRState()
371 m_state.SetError(e_regSetGPR, Read, 0); in GetGPRState()
374 m_state.SetError( in GetGPRState()
377 (thread_state_t)&m_state.context.gpr, &count)); in GetGPRState()
380 return m_state.GetError(e_regSetGPR, Read); in GetGPRState()
387 if (force || m_state.GetError(e_regSetFPU, Read)) { in GetFPUState()
390 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1; in GetFPUState()
391 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1; in GetFPUState()
392 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234; in GetFPUState()
393 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678; in GetFPUState()
394 m_state.context.fpu.no_avx.__fpu_ftw = 1; in GetFPUState()
395 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX; in GetFPUState()
396 m_state.context.fpu.no_avx.__fpu_fop = 2; in GetFPUState()
397 m_state.context.fpu.no_avx.__fpu_ip = 3; in GetFPUState()
398 m_state.context.fpu.no_avx.__fpu_cs = 4; in GetFPUState()
399 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5; in GetFPUState()
400 m_state.context.fpu.no_avx.__fpu_dp = 6; in GetFPUState()
401 m_state.context.fpu.no_avx.__fpu_ds = 7; in GetFPUState()
402 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX; in GetFPUState()
403 m_state.context.fpu.no_avx.__fpu_mxcsr = 8; in GetFPUState()
404 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9; in GetFPUState()
407 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a'; in GetFPUState()
408 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b'; in GetFPUState()
409 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c'; in GetFPUState()
410 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd'; in GetFPUState()
411 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e'; in GetFPUState()
412 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f'; in GetFPUState()
413 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g'; in GetFPUState()
414 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h'; in GetFPUState()
416 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; in GetFPUState()
417 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; in GetFPUState()
418 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; in GetFPUState()
419 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; in GetFPUState()
420 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; in GetFPUState()
421 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; in GetFPUState()
422 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; in GetFPUState()
423 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; in GetFPUState()
426 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0'; in GetFPUState()
427 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1'; in GetFPUState()
428 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2'; in GetFPUState()
429 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3'; in GetFPUState()
430 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4'; in GetFPUState()
431 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5'; in GetFPUState()
432 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6'; in GetFPUState()
433 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7'; in GetFPUState()
435 for (int i = 0; i < sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i) in GetFPUState()
436 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN; in GetFPUState()
437 m_state.context.fpu.no_avx.__fpu_reserved1 = -1; in GetFPUState()
440 for (int i = 0; i < sizeof(m_state.context.fpu.avx.__avx_reserved1); in GetFPUState()
442 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN; in GetFPUState()
445 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0'; in GetFPUState()
446 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1'; in GetFPUState()
447 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2'; in GetFPUState()
448 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3'; in GetFPUState()
449 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4'; in GetFPUState()
450 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5'; in GetFPUState()
451 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6'; in GetFPUState()
452 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7'; in GetFPUState()
457 m_state.context.fpu.avx512f.__fpu_k0.__opmask_reg[i] = '0'; in GetFPUState()
458 m_state.context.fpu.avx512f.__fpu_k1.__opmask_reg[i] = '1'; in GetFPUState()
459 m_state.context.fpu.avx512f.__fpu_k2.__opmask_reg[i] = '2'; in GetFPUState()
460 m_state.context.fpu.avx512f.__fpu_k3.__opmask_reg[i] = '3'; in GetFPUState()
461 m_state.context.fpu.avx512f.__fpu_k4.__opmask_reg[i] = '4'; in GetFPUState()
462 m_state.context.fpu.avx512f.__fpu_k5.__opmask_reg[i] = '5'; in GetFPUState()
463 m_state.context.fpu.avx512f.__fpu_k6.__opmask_reg[i] = '6'; in GetFPUState()
464 m_state.context.fpu.avx512f.__fpu_k7.__opmask_reg[i] = '7'; in GetFPUState()
468 m_state.context.fpu.avx512f.__fpu_zmmh0.__ymm_reg[i] = '0'; in GetFPUState()
469 m_state.context.fpu.avx512f.__fpu_zmmh1.__ymm_reg[i] = '1'; in GetFPUState()
470 m_state.context.fpu.avx512f.__fpu_zmmh2.__ymm_reg[i] = '2'; in GetFPUState()
471 m_state.context.fpu.avx512f.__fpu_zmmh3.__ymm_reg[i] = '3'; in GetFPUState()
472 m_state.context.fpu.avx512f.__fpu_zmmh4.__ymm_reg[i] = '4'; in GetFPUState()
473 m_state.context.fpu.avx512f.__fpu_zmmh5.__ymm_reg[i] = '5'; in GetFPUState()
474 m_state.context.fpu.avx512f.__fpu_zmmh6.__ymm_reg[i] = '6'; in GetFPUState()
475 m_state.context.fpu.avx512f.__fpu_zmmh7.__ymm_reg[i] = '7'; in GetFPUState()
478 m_state.SetError(e_regSetFPU, Read, 0); in GetFPUState()
491 m_state.SetError(e_regSetFPU, Read, in GetFPUState()
493 (thread_state_t)&m_state.context.fpu, in GetFPUState()
498 m_state.GetError(e_regSetFPU, Read)); in GetFPUState()
499 if (m_state.GetError(e_regSetFPU, Read) == KERN_SUCCESS) in GetFPUState()
500 return m_state.GetError(e_regSetFPU, Read); in GetFPUState()
506 m_state.SetError(e_regSetFPU, Read, in GetFPUState()
508 (thread_state_t)&m_state.context.fpu, in GetFPUState()
513 m_state.GetError(e_regSetFPU, Read)); in GetFPUState()
516 return m_state.GetError(e_regSetFPU, Read); in GetFPUState()
520 if (force || m_state.GetError(e_regSetEXC, Read)) { in GetEXCState()
522 m_state.SetError( in GetEXCState()
525 (thread_state_t)&m_state.context.exc, &count)); in GetEXCState()
527 return m_state.GetError(e_regSetEXC, Read); in GetEXCState()
537 m_state.SetError(e_regSetGPR, Write, in SetGPRState()
540 (thread_state_t)&m_state.context.gpr, in SetGPRState()
542 return m_state.GetError(e_regSetGPR, Write); in SetGPRState()
547 m_state.SetError(e_regSetFPU, Write, 0); in SetFPUState()
548 return m_state.GetError(e_regSetFPU, Write); in SetFPUState()
561 m_state.SetError(e_regSetFPU, Write, in SetFPUState()
563 (thread_state_t)&m_state.context.fpu, in SetFPUState()
565 return m_state.GetError(e_regSetFPU, Write); in SetFPUState()
570 m_state.SetError(e_regSetEXC, Write, in SetEXCState()
573 (thread_state_t)&m_state.context.exc, in SetEXCState()
575 return m_state.GetError(e_regSetEXC, Write); in SetEXCState()
579 if (force || m_state.GetError(e_regSetDBG, Read)) { in GetDBGState()
581 m_state.SetError( in GetDBGState()
584 (thread_state_t)&m_state.context.dbg, &count)); in GetDBGState()
586 return m_state.GetError(e_regSetDBG, Read); in GetDBGState()
590 m_state.SetError(e_regSetDBG, Write, in SetDBGState()
593 (thread_state_t)&m_state.context.dbg, in SetDBGState()
598 (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG); in SetDBGState()
605 return m_state.GetError(e_regSetDBG, Write); in SetDBGState()
623 DBG &debug_state = m_state.context.dbg; in ThreadWillResume()
642 m_state.InvalidateAllRegisterStates(); in ThreadDidStop()
687 if (m_state.context.gpr.__eip > 0) { in NotifyException()
688 m_state.context.gpr.__eip = static_cast<uint32_t>(pc); in NotifyException()
871 DBG &debug_state = m_state.context.dbg; in EnableHardwareBreakpoint()
907 m_state.context.dbg = GetDBGCheckpoint(); in EnableHardwareBreakpoint()
926 DBG &debug_state = m_state.context.dbg; in DisableHardwareBreakpoint()
944 m_state.context.dbg = GetDBGCheckpoint(); in DisableHardwareBreakpoint()
1026 m_2pc_dbg_checkpoint = m_state.context.dbg; in StartTransForHWP()
1031 m_state.context.dbg = m_2pc_dbg_checkpoint; in RollbackTransForHWP()
1077 DBG &debug_state = m_state.context.dbg; in EnableHardwareWatchpoint()
1100 m_state.context.dbg = GetDBGCheckpoint(); in EnableHardwareWatchpoint()
1117 DBG &debug_state = m_state.context.dbg; in DisableHardwareWatchpoint()
1134 m_state.context.dbg = GetDBGCheckpoint(); in DisableHardwareWatchpoint()
1149 DBG &debug_state = m_state.context.dbg; in GetHardwareWatchpointHit()
1170 m_state.context.gpr.__eflags |= trace_bit; in EnableHardwareSingleStep()
1172 m_state.context.gpr.__eflags &= ~trace_bit; in EnableHardwareSingleStep()
1175 return m_state.GetError(e_regSetGPR, Read); in EnableHardwareSingleStep()
1790 value->value.uint32 = ((uint32_t *)(&m_state.context.gpr))[reg]; in GetRegisterValue()
1803 *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); in GetRegisterValue()
1807 *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); in GetRegisterValue()
1810 memcpy (&value->value.uint16, &m_state.context.fpu.no_avx.__fpu_ftw, 2); in GetRegisterValue()
1813 value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; in GetRegisterValue()
1816 value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; in GetRegisterValue()
1819 value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; in GetRegisterValue()
1822 value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; in GetRegisterValue()
1825 value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; in GetRegisterValue()
1828 value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; in GetRegisterValue()
1831 value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; in GetRegisterValue()
1836 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, 10); in GetRegisterValue()
1840 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, 10); in GetRegisterValue()
1844 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, 10); in GetRegisterValue()
1848 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, 10); in GetRegisterValue()
1852 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, 10); in GetRegisterValue()
1856 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, 10); in GetRegisterValue()
1860 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, 10); in GetRegisterValue()
1864 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, 10); in GetRegisterValue()
1869 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, 16); in GetRegisterValue()
1873 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, 16); in GetRegisterValue()
1877 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, 16); in GetRegisterValue()
1881 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, 16); in GetRegisterValue()
1885 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, 16); in GetRegisterValue()
1889 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, 16); in GetRegisterValue()
1893 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, 16); in GetRegisterValue()
1897 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, 16); in GetRegisterValue()
1901 memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, \ in GetRegisterValue()
1904 m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, 16); in GetRegisterValue()
1940 &m_state.context.fpu.avx512f.__fpu_k0 + (reg - fpu_k0), 8); in GetRegisterValue()
1951 &m_state.context.fpu.avx512f.__fpu_xmm0 + (reg - fpu_zmm0), 16); in GetRegisterValue()
1953 &m_state.context.fpu.avx512f.__fpu_ymmh0 + (reg - fpu_zmm0), 16); in GetRegisterValue()
1955 &m_state.context.fpu.avx512f.__fpu_zmmh0 + (reg - fpu_zmm0), 32); in GetRegisterValue()
1962 value->value.uint32 = (&m_state.context.exc.__trapno)[reg]; in GetRegisterValue()
2010 ((uint32_t *)(&m_state.context.gpr))[reg] = value->value.uint32; in SetRegisterValue()
2022 *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = in SetRegisterValue()
2027 *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = in SetRegisterValue()
2032 memcpy (&m_state.context.fpu.no_avx.__fpu_ftw, &value->value.uint16, 2); in SetRegisterValue()
2036 m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; in SetRegisterValue()
2040 m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; in SetRegisterValue()
2044 m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; in SetRegisterValue()
2048 m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; in SetRegisterValue()
2052 m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; in SetRegisterValue()
2056 m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; in SetRegisterValue()
2060 m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; in SetRegisterValue()
2065 memcpy(m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, in SetRegisterValue()
2070 memcpy(m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, in SetRegisterValue()
2075 memcpy(m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, in SetRegisterValue()
2080 memcpy(m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, in SetRegisterValue()
2085 memcpy(m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, in SetRegisterValue()
2090 memcpy(m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, in SetRegisterValue()
2095 memcpy(m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, in SetRegisterValue()
2100 memcpy(m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, in SetRegisterValue()
2106 memcpy(m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, in SetRegisterValue()
2111 memcpy(m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, in SetRegisterValue()
2116 memcpy(m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, in SetRegisterValue()
2121 memcpy(m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, in SetRegisterValue()
2126 memcpy(m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, in SetRegisterValue()
2131 memcpy(m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, in SetRegisterValue()
2136 memcpy(m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, in SetRegisterValue()
2141 memcpy(m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, in SetRegisterValue()
2147 memcpy(m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, &value->value.uint8, \ in SetRegisterValue()
2149 memcpy(m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, \ in SetRegisterValue()
2185 memcpy(&m_state.context.fpu.avx512f.__fpu_k0 + (reg - fpu_k0), in SetRegisterValue()
2196 memcpy(&m_state.context.fpu.avx512f.__fpu_xmm0 + (reg - fpu_zmm0), in SetRegisterValue()
2198 memcpy(&m_state.context.fpu.avx512f.__fpu_ymmh0 + (reg - fpu_zmm0), in SetRegisterValue()
2200 memcpy(&m_state.context.fpu.avx512f.__fpu_zmmh0 + (reg - fpu_zmm0), in SetRegisterValue()
2208 (&m_state.context.exc.__trapno)[reg] = value->value.uint32; in SetRegisterValue()
2282 memcpy(p, &m_state.context.gpr, sizeof(GPR)); in GetRegisterContext()
2286 memcpy(p, &m_state.context.fpu.no_avx.__fpu_fcw, 5); in GetRegisterContext()
2288 memcpy(p, &m_state.context.fpu.no_avx.__fpu_fop, 8); in GetRegisterContext()
2290 memcpy(p, &m_state.context.fpu.no_avx.__fpu_dp, 6); in GetRegisterContext()
2292 memcpy(p, &m_state.context.fpu.no_avx.__fpu_mxcsr, 8); in GetRegisterContext()
2298 memcpy(p, &m_state.context.fpu.no_avx.__fpu_stmm0 + i, 10); in GetRegisterContext()
2304 memcpy(p, &m_state.context.fpu.avx512f.__fpu_k0 + i, 8); in GetRegisterContext()
2312 memcpy(p, &m_state.context.fpu.avx.__fpu_xmm0 + i, 16); in GetRegisterContext()
2314 memcpy(p, &m_state.context.fpu.avx.__fpu_ymmh0 + i, 16); in GetRegisterContext()
2319 memcpy(p, &m_state.context.fpu.avx512f.__fpu_zmmh0 + i, 32); in GetRegisterContext()
2325 memcpy(p, &m_state.context.fpu.no_avx.__fpu_xmm0, 8 * 16); in GetRegisterContext()
2330 memcpy(p, &m_state.context.exc, sizeof(EXC)); in GetRegisterContext()
2349 nub_size_t size = sizeof(m_state.context); in SetRegisterContext()
2359 memcpy(&m_state.context.gpr, p, sizeof(GPR)); in SetRegisterContext()
2363 memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5); in SetRegisterContext()
2365 memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8); in SetRegisterContext()
2367 memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6); in SetRegisterContext()
2369 memcpy(&m_state.context.fpu.no_avx.__fpu_mxcsr, p, 8); in SetRegisterContext()
2375 memcpy(&m_state.context.fpu.no_avx.__fpu_stmm0 + i, p, 10); in SetRegisterContext()
2381 memcpy(&m_state.context.fpu.avx512f.__fpu_k0 + i, p, 8); in SetRegisterContext()
2389 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + i, p, 16); in SetRegisterContext()
2391 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + i, p, 16); in SetRegisterContext()
2397 memcpy(&m_state.context.fpu.avx512f.__fpu_zmmh0 + i, p, 32); in SetRegisterContext()
2403 memcpy(&m_state.context.fpu.no_avx.__fpu_xmm0, p, 8 * 16); in SetRegisterContext()
2408 memcpy(&m_state.context.exc, p, sizeof(EXC)); in SetRegisterContext()
2458 m_saved_register_states[save_id] = m_state.context; in SaveRegisterState()
2466 m_state.context.gpr = pos->second.gpr; in RestoreRegisterState()
2467 m_state.context.fpu = pos->second.fpu; in RestoreRegisterState()
2468 m_state.context.exc = pos->second.exc; in RestoreRegisterState()
2469 m_state.SetError(e_regSetGPR, Read, 0); in RestoreRegisterState()
2470 m_state.SetError(e_regSetFPU, Read, 0); in RestoreRegisterState()
2471 m_state.SetError(e_regSetEXC, Read, 0); in RestoreRegisterState()
2529 return m_state.RegsAreValid(set); in RegisterSetStateIsValid()