Lines Matching refs:NULL
1182 e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, 0, \
1188 e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 1, INVALID_NUB_REGNUM, \
1194 e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 0, INVALID_NUB_REGNUM, \
1213 #define GPR_SIZE(reg) (sizeof(((DNBArchImplI386::GPR *)NULL)->__##reg))
1214 #define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg))
1216 (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg.__mmst_reg))
1218 (sizeof(((DNBArchImplI386::FPU *)NULL)->__fpu_##reg.__xmm_reg))
1221 #define EXC_SIZE(reg) (sizeof(((DNBArchImplI386::EXC *)NULL)->__##reg))
1238 const char *g_contained_eax[] = {"eax", NULL};
1239 const char *g_contained_ebx[] = {"ebx", NULL};
1240 const char *g_contained_ecx[] = {"ecx", NULL};
1241 const char *g_contained_edx[] = {"edx", NULL};
1242 const char *g_contained_edi[] = {"edi", NULL};
1243 const char *g_contained_esi[] = {"esi", NULL};
1244 const char *g_contained_ebp[] = {"ebp", NULL};
1245 const char *g_contained_esp[] = {"esp", NULL};
1247 const char *g_invalidate_eax[] = {"eax", "ax", "ah", "al", NULL};
1248 const char *g_invalidate_ebx[] = {"ebx", "bx", "bh", "bl", NULL};
1249 const char *g_invalidate_ecx[] = {"ecx", "cx", "ch", "cl", NULL};
1250 const char *g_invalidate_edx[] = {"edx", "dx", "dh", "dl", NULL};
1251 const char *g_invalidate_edi[] = {"edi", "di", "dil", NULL};
1252 const char *g_invalidate_esi[] = {"esi", "si", "sil", NULL};
1253 const char *g_invalidate_ebp[] = {"ebp", "bp", "bpl", NULL};
1254 const char *g_invalidate_esp[] = {"esp", "sp", "spl", NULL};
1258 {e_regSetGPR, gpr_eax, "eax", NULL, Uint, Hex, GPR_SIZE(eax),
1260 debugserver_eax, NULL, g_invalidate_eax},
1261 {e_regSetGPR, gpr_ebx, "ebx", NULL, Uint, Hex, GPR_SIZE(ebx),
1263 debugserver_ebx, NULL, g_invalidate_ebx},
1264 {e_regSetGPR, gpr_ecx, "ecx", NULL, Uint, Hex, GPR_SIZE(ecx),
1266 debugserver_ecx, NULL, g_invalidate_ecx},
1267 {e_regSetGPR, gpr_edx, "edx", NULL, Uint, Hex, GPR_SIZE(edx),
1269 debugserver_edx, NULL, g_invalidate_edx},
1270 {e_regSetGPR, gpr_edi, "edi", NULL, Uint, Hex, GPR_SIZE(edi),
1272 debugserver_edi, NULL, g_invalidate_edi},
1273 {e_regSetGPR, gpr_esi, "esi", NULL, Uint, Hex, GPR_SIZE(esi),
1275 debugserver_esi, NULL, g_invalidate_esi},
1278 debugserver_ebp, NULL, g_invalidate_ebp},
1281 debugserver_esp, NULL, g_invalidate_esp},
1282 {e_regSetGPR, gpr_ss, "ss", NULL, Uint, Hex, GPR_SIZE(ss), GPR_OFFSET(ss),
1284 NULL, NULL},
1287 debugserver_eflags, NULL, NULL},
1290 debugserver_eip, NULL, NULL},
1291 {e_regSetGPR, gpr_cs, "cs", NULL, Uint, Hex, GPR_SIZE(cs), GPR_OFFSET(cs),
1293 NULL, NULL},
1294 {e_regSetGPR, gpr_ds, "ds", NULL, Uint, Hex, GPR_SIZE(ds), GPR_OFFSET(ds),
1296 NULL, NULL},
1297 {e_regSetGPR, gpr_es, "es", NULL, Uint, Hex, GPR_SIZE(es), GPR_OFFSET(es),
1299 NULL, NULL},
1300 {e_regSetGPR, gpr_fs, "fs", NULL, Uint, Hex, GPR_SIZE(fs), GPR_OFFSET(fs),
1302 NULL, NULL},
1303 {e_regSetGPR, gpr_gs, "gs", NULL, Uint, Hex, GPR_SIZE(gs), GPR_OFFSET(gs),
1305 NULL, NULL},
1328 {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
1330 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1331 {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
1333 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1334 {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
1336 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1337 {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
1339 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1340 {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
1342 INVALID_NUB_REGNUM, NULL, NULL},
1343 {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
1345 INVALID_NUB_REGNUM, NULL, NULL},
1346 {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
1348 INVALID_NUB_REGNUM, NULL, NULL},
1349 {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
1351 INVALID_NUB_REGNUM, NULL, NULL},
1352 {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
1354 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1355 {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
1357 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1361 INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
1364 INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
1367 INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
1370 INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
1373 INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
1376 INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
1379 INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
1382 INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
1384 {e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8,
1386 INVALID_NUB_REGNUM, debugserver_xmm0, NULL, NULL},
1387 {e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8,
1389 INVALID_NUB_REGNUM, debugserver_xmm1, NULL, NULL},
1390 {e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8,
1392 INVALID_NUB_REGNUM, debugserver_xmm2, NULL, NULL},
1393 {e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8,
1395 INVALID_NUB_REGNUM, debugserver_xmm3, NULL, NULL},
1396 {e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8,
1398 INVALID_NUB_REGNUM, debugserver_xmm4, NULL, NULL},
1399 {e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8,
1401 INVALID_NUB_REGNUM, debugserver_xmm5, NULL, NULL},
1402 {e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8,
1404 INVALID_NUB_REGNUM, debugserver_xmm6, NULL, NULL},
1405 {e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8,
1407 INVALID_NUB_REGNUM, debugserver_xmm7, NULL, NULL}};
1409 static const char *g_contained_ymm0[] = {"ymm0", NULL};
1410 static const char *g_contained_ymm1[] = {"ymm1", NULL};
1411 static const char *g_contained_ymm2[] = {"ymm2", NULL};
1412 static const char *g_contained_ymm3[] = {"ymm3", NULL};
1413 static const char *g_contained_ymm4[] = {"ymm4", NULL};
1414 static const char *g_contained_ymm5[] = {"ymm5", NULL};
1415 static const char *g_contained_ymm6[] = {"ymm6", NULL};
1416 static const char *g_contained_ymm7[] = {"ymm7", NULL};
1419 {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
1421 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1422 {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
1424 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1425 {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
1427 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1428 {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
1430 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1431 {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
1433 INVALID_NUB_REGNUM, NULL, NULL},
1434 {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
1436 INVALID_NUB_REGNUM, NULL, NULL},
1437 {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
1439 INVALID_NUB_REGNUM, NULL, NULL},
1440 {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
1442 INVALID_NUB_REGNUM, NULL, NULL},
1443 {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
1445 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1446 {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
1448 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1452 INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
1455 INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
1458 INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
1461 INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
1464 INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
1467 INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
1470 INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
1473 INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
1475 {e_regSetFPU, fpu_ymm0, "ymm0", NULL, Vector, VectorOfUInt8,
1477 INVALID_NUB_REGNUM, debugserver_ymm0, NULL, NULL},
1478 {e_regSetFPU, fpu_ymm1, "ymm1", NULL, Vector, VectorOfUInt8,
1480 INVALID_NUB_REGNUM, debugserver_ymm1, NULL, NULL},
1481 {e_regSetFPU, fpu_ymm2, "ymm2", NULL, Vector, VectorOfUInt8,
1483 INVALID_NUB_REGNUM, debugserver_ymm2, NULL, NULL},
1484 {e_regSetFPU, fpu_ymm3, "ymm3", NULL, Vector, VectorOfUInt8,
1486 INVALID_NUB_REGNUM, debugserver_ymm3, NULL, NULL},
1487 {e_regSetFPU, fpu_ymm4, "ymm4", NULL, Vector, VectorOfUInt8,
1489 INVALID_NUB_REGNUM, debugserver_ymm4, NULL, NULL},
1490 {e_regSetFPU, fpu_ymm5, "ymm5", NULL, Vector, VectorOfUInt8,
1492 INVALID_NUB_REGNUM, debugserver_ymm5, NULL, NULL},
1493 {e_regSetFPU, fpu_ymm6, "ymm6", NULL, Vector, VectorOfUInt8,
1495 INVALID_NUB_REGNUM, debugserver_ymm6, NULL, NULL},
1496 {e_regSetFPU, fpu_ymm7, "ymm7", NULL, Vector, VectorOfUInt8,
1498 INVALID_NUB_REGNUM, debugserver_ymm7, NULL, NULL},
1500 {e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8,
1502 debugserver_xmm0, g_contained_ymm0, NULL},
1503 {e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8,
1505 debugserver_xmm1, g_contained_ymm1, NULL},
1506 {e_regSetFPU, fpu_xmm2, "xmm2", NULL, Vector, VectorOfUInt8,
1508 debugserver_xmm2, g_contained_ymm2, NULL},
1509 {e_regSetFPU, fpu_xmm3, "xmm3", NULL, Vector, VectorOfUInt8,
1511 debugserver_xmm3, g_contained_ymm3, NULL},
1512 {e_regSetFPU, fpu_xmm4, "xmm4", NULL, Vector, VectorOfUInt8,
1514 debugserver_xmm4, g_contained_ymm4, NULL},
1515 {e_regSetFPU, fpu_xmm5, "xmm5", NULL, Vector, VectorOfUInt8,
1517 debugserver_xmm5, g_contained_ymm5, NULL},
1518 {e_regSetFPU, fpu_xmm6, "xmm6", NULL, Vector, VectorOfUInt8,
1520 debugserver_xmm6, g_contained_ymm6, NULL},
1521 {e_regSetFPU, fpu_xmm7, "xmm7", NULL, Vector, VectorOfUInt8,
1523 debugserver_xmm7, g_contained_ymm7, NULL},
1532 e_regSetFPU, fpu_zmm##reg, STR(zmm##reg), NULL, Vector, VectorOfUInt8, \
1534 dwarf_zmm##reg, INVALID_NUB_REGNUM, debugserver_zmm##reg, NULL, NULL \
1539 e_regSetFPU, fpu_ymm##reg, STR(ymm##reg), NULL, Vector, VectorOfUInt8, \
1541 INVALID_NUB_REGNUM, debugserver_ymm##reg, g_contained_zmm##reg, NULL \
1546 e_regSetFPU, fpu_xmm##reg, STR(xmm##reg), NULL, Vector, VectorOfUInt8, \
1548 INVALID_NUB_REGNUM, debugserver_xmm##reg, g_contained_zmm##reg, NULL \
1553 e_regSetFPU, fpu_k##reg, STR(k##reg), NULL, Vector, VectorOfUInt8, 8, \
1555 debugserver_k##reg, NULL, NULL \
1558 static const char *g_contained_zmm0[] = {"zmm0", NULL};
1559 static const char *g_contained_zmm1[] = {"zmm1", NULL};
1560 static const char *g_contained_zmm2[] = {"zmm2", NULL};
1561 static const char *g_contained_zmm3[] = {"zmm3", NULL};
1562 static const char *g_contained_zmm4[] = {"zmm4", NULL};
1563 static const char *g_contained_zmm5[] = {"zmm5", NULL};
1564 static const char *g_contained_zmm6[] = {"zmm6", NULL};
1565 static const char *g_contained_zmm7[] = {"zmm7", NULL};
1568 {e_regSetFPU, fpu_fcw, "fctrl", NULL, Uint, Hex, FPU_SIZE_UINT(fcw),
1570 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1571 {e_regSetFPU, fpu_fsw, "fstat", NULL, Uint, Hex, FPU_SIZE_UINT(fsw),
1573 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1574 {e_regSetFPU, fpu_ftw, "ftag", NULL, Uint, Hex, 2 /* sizeof __fpu_ftw + sizeof __fpu_rsrv1 */,
1576 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1577 {e_regSetFPU, fpu_fop, "fop", NULL, Uint, Hex, FPU_SIZE_UINT(fop),
1579 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1580 {e_regSetFPU, fpu_ip, "fioff", NULL, Uint, Hex, FPU_SIZE_UINT(ip),
1582 INVALID_NUB_REGNUM, NULL, NULL},
1583 {e_regSetFPU, fpu_cs, "fiseg", NULL, Uint, Hex, FPU_SIZE_UINT(cs),
1585 INVALID_NUB_REGNUM, NULL, NULL},
1586 {e_regSetFPU, fpu_dp, "fooff", NULL, Uint, Hex, FPU_SIZE_UINT(dp),
1588 INVALID_NUB_REGNUM, NULL, NULL},
1589 {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
1591 INVALID_NUB_REGNUM, NULL, NULL},
1592 {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
1594 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1595 {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
1597 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1601 INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
1604 INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
1607 INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
1610 INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
1613 INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
1616 INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
1619 INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
1622 INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
1663 {e_regSetEXC, exc_trapno, "trapno", NULL, Uint, Hex, EXC_SIZE(trapno),
1665 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1666 {e_regSetEXC, exc_err, "err", NULL, Uint, Hex, EXC_SIZE(err),
1668 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
1669 {e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex,
1671 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}};
1695 {"i386 Registers", NULL, k_num_all_registers_no_avx},
1702 {"i386 Registers", NULL, k_num_all_registers_avx},
1708 {"i386 Registers", NULL, k_num_all_registers_avx512f},
1727 return NULL; in SoftwareBreakpointOpcode()
2225 if (g_fpu_registers_avx512f[i].value_regs == NULL) in GetRegisterContextSize()
2231 if (g_fpu_registers_avx[i].value_regs == NULL) in GetRegisterContextSize()
2236 if (g_fpu_registers_no_avx[i].value_regs == NULL) in GetRegisterContextSize()
2350 if (buf == NULL || buf_len == 0) in SetRegisterContext()