Lines Matching refs:control
88 m_hbp_regs[bp_index].control = control_value; in SetHardwareBreakpoint()
95 m_hbp_regs[bp_index].control &= ~1; in SetHardwareBreakpoint()
125 uint32_t tempControl = m_hbp_regs[hw_idx].control; in ClearHardwareBreakpoint()
127 m_hbp_regs[hw_idx].control &= ~g_enable_bit; in ClearHardwareBreakpoint()
134 m_hbp_regs[hw_idx].control = tempControl; in ClearHardwareBreakpoint()
181 uint32_t tempControl = m_hbp_regs[i].control; in ClearAllHardwareBreakpoints()
184 m_hbp_regs[i].control &= ~g_enable_bit; in ClearAllHardwareBreakpoints()
191 m_hbp_regs[i].control = tempControl; in ClearAllHardwareBreakpoints()
203 if ((m_hbp_regs[bp_index].control & g_enable_bit) != 0) in BreakpointIsEnabled()
296 m_hwp_regs[wp_index].control = control_value; in SetHardwareWatchpoint()
303 m_hwp_regs[wp_index].control &= ~g_enable_bit; in SetHardwareWatchpoint()
333 uint32_t tempControl = m_hwp_regs[wp_index].control; in ClearHardwareWatchpoint()
336 m_hwp_regs[wp_index].control &= ~g_enable_bit; in ClearHardwareWatchpoint()
343 m_hwp_regs[wp_index].control = tempControl; in ClearHardwareWatchpoint()
365 uint32_t tempControl = m_hwp_regs[i].control; in ClearAllHardwareWatchpoints()
368 m_hwp_regs[i].control &= ~g_enable_bit; in ClearAllHardwareWatchpoints()
375 m_hwp_regs[i].control = tempControl; in ClearAllHardwareWatchpoints()
391 switch ((m_hwp_regs[wp_index].control >> 5) & 0xff) { in GetWatchpointSize()
409 if ((m_hwp_regs[wp_index].control & g_enable_bit) != 0) in WatchpointIsEnabled()