321     if ((m_hbr_regs[i].control & 1) == 0) {  in SetHardwareBreakpoint()
334   m_hbr_regs[bp_index].control = control_value;  in SetHardwareBreakpoint()
341     m_hbr_regs[bp_index].control &= ~1;  in SetHardwareBreakpoint()
364   uint32_t tempControl = m_hbr_regs[hw_idx].control;  in ClearHardwareBreakpoint()
366   m_hbr_regs[hw_idx].control &= ~1;  in ClearHardwareBreakpoint()
373     m_hbr_regs[hw_idx].control = tempControl;  in ClearHardwareBreakpoint()
393     if ((m_hbr_regs[bp_index].control & 0x1) && (trap_addr == break_addr)) {  in GetHardwareBreakHitIndex()
420     if (m_hbr_regs[i].control & 0x01) {  in ClearAllHardwareBreakpoints()
423       tempControl = m_hbr_regs[i].control;  in ClearAllHardwareBreakpoints()
426       m_hbr_regs[i].control &= ~1;  in ClearAllHardwareBreakpoints()
433         m_hbr_regs[i].control = tempControl;  in ClearAllHardwareBreakpoints()
534     if ((m_hwp_regs[i].control & 1) == 0) {  in SetHardwareWatchpoint()
547   m_hwp_regs[wp_index].control = control_value;  in SetHardwareWatchpoint()
554     m_hwp_regs[wp_index].control &= ~1;  in SetHardwareWatchpoint()
578   uint32_t tempControl = m_hwp_regs[wp_index].control;  in ClearHardwareWatchpoint()
581   m_hwp_regs[wp_index].control &= ~1;  in ClearHardwareWatchpoint()
588     m_hwp_regs[wp_index].control = tempControl;  in ClearHardwareWatchpoint()
608     if (m_hwp_regs[i].control & 0x01) {  in ClearAllHardwareWatchpoints()
611       tempControl = m_hwp_regs[i].control;  in ClearAllHardwareWatchpoints()
614       m_hwp_regs[i].control &= ~1;  in ClearAllHardwareWatchpoints()
621         m_hwp_regs[i].control = tempControl;  in ClearAllHardwareWatchpoints()
636   switch ((m_hwp_regs[wp_index].control >> 5) & 0x0f) {  in GetWatchpointSize()
653   if ((m_hwp_regs[wp_index].control & 0x1) == 0x1)  in WatchpointIsEnabled()
743     ctrl_buf = &m_hwp_regs[hwb_index].control;  in WriteHardwareDebugRegs()
759     ctrl_buf = &m_hbr_regs[hwb_index].control;  in WriteHardwareDebugRegs()