Lines Matching refs:EmulateInstructionMIPS64
43 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionMIPS64, InstructionMIPS64) in LLDB_PLUGIN_DEFINE_ADV() argument
62 EmulateInstructionMIPS64::EmulateInstructionMIPS64( in EmulateInstructionMIPS64() function in EmulateInstructionMIPS64
174 void EmulateInstructionMIPS64::Initialize() { in Initialize()
179 void EmulateInstructionMIPS64::Terminate() { in Terminate()
183 llvm::StringRef EmulateInstructionMIPS64::GetPluginDescriptionStatic() { in GetPluginDescriptionStatic()
188 EmulateInstructionMIPS64::CreateInstance(const ArchSpec &arch, in CreateInstance()
190 if (EmulateInstructionMIPS64::SupportsEmulatingInstructionsOfTypeStatic( in CreateInstance()
194 return new EmulateInstructionMIPS64(arch); in CreateInstance()
201 bool EmulateInstructionMIPS64::SetTargetTriple(const ArchSpec &arch) { in SetTargetTriple()
206 const char *EmulateInstructionMIPS64::GetRegisterName(unsigned reg_num, in GetRegisterName()
575 bool EmulateInstructionMIPS64::GetRegisterInfo(RegisterKind reg_kind, in GetRegisterInfo()
657 EmulateInstructionMIPS64::MipsOpcode *
658 EmulateInstructionMIPS64::GetOpcodeForInstruction(llvm::StringRef op_name) { in GetOpcodeForInstruction()
659 static EmulateInstructionMIPS64::MipsOpcode g_opcodes[] = { in GetOpcodeForInstruction()
661 {"DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, in GetOpcodeForInstruction()
663 {"ADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, in GetOpcodeForInstruction()
665 {"SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt, offset(rs)"}, in GetOpcodeForInstruction()
666 {"LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt, offset(base)"}, in GetOpcodeForInstruction()
667 {"DSUBU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU, in GetOpcodeForInstruction()
669 {"SUBU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU, in GetOpcodeForInstruction()
671 {"DADDU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU, in GetOpcodeForInstruction()
673 {"ADDU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU, in GetOpcodeForInstruction()
675 {"LUI", &EmulateInstructionMIPS64::Emulate_LUI, "LUI rt, immediate"}, in GetOpcodeForInstruction()
685 {"LB", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
687 {"LBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
689 {"LBU", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
691 {"LBUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
693 {"LDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
695 {"LDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
697 {"LDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
699 {"LLD", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
701 {"LDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
703 {"LDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, in GetOpcodeForInstruction()
705 {"LH", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
707 {"LHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
709 {"LHU", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
711 {"LHUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
713 {"LL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
715 {"LLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
717 {"LUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, in GetOpcodeForInstruction()
719 {"LW", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
721 {"LWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
723 {"LWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
725 {"LWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
727 {"LWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
729 {"LWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
731 {"LWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
733 {"LWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
735 {"LWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, in GetOpcodeForInstruction()
738 {"SB", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
740 {"SBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
742 {"SC", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
744 {"SCE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
746 {"SCD", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
748 {"SDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
750 {"SDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
752 {"SDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
754 {"SDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
756 {"SDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, in GetOpcodeForInstruction()
758 {"SH", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
760 {"SHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
762 {"SUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, in GetOpcodeForInstruction()
764 {"SW", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
766 {"SWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
768 {"SWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
770 {"SWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
772 {"SWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
774 {"SWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
776 {"SWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
778 {"SWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, in GetOpcodeForInstruction()
780 {"SWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, in GetOpcodeForInstruction()
784 {"BEQ", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset"}, in GetOpcodeForInstruction()
785 {"BEQ64", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset"}, in GetOpcodeForInstruction()
786 {"BNE", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset"}, in GetOpcodeForInstruction()
787 {"BNE64", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset"}, in GetOpcodeForInstruction()
788 {"BEQL", &EmulateInstructionMIPS64::Emulate_BXX_3ops, in GetOpcodeForInstruction()
790 {"BNEL", &EmulateInstructionMIPS64::Emulate_BXX_3ops, in GetOpcodeForInstruction()
792 {"BGEZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link, in GetOpcodeForInstruction()
794 {"BAL", &EmulateInstructionMIPS64::Emulate_BAL, "BAL offset"}, in GetOpcodeForInstruction()
795 {"BGEZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link, in GetOpcodeForInstruction()
797 {"BALC", &EmulateInstructionMIPS64::Emulate_BALC, "BALC offset"}, in GetOpcodeForInstruction()
798 {"BC", &EmulateInstructionMIPS64::Emulate_BC, "BC offset"}, in GetOpcodeForInstruction()
799 {"BGEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset"}, in GetOpcodeForInstruction()
800 {"BGEZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset"}, in GetOpcodeForInstruction()
801 {"BLEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C, in GetOpcodeForInstruction()
803 {"BGEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C, in GetOpcodeForInstruction()
805 {"BLTZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C, in GetOpcodeForInstruction()
807 {"BGTZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C, in GetOpcodeForInstruction()
809 {"BEQZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C, in GetOpcodeForInstruction()
811 {"BNEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C, in GetOpcodeForInstruction()
813 {"BEQC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
815 {"BEQC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
817 {"BNEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
819 {"BNEC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
821 {"BLTC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
823 {"BLTC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
825 {"BGEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
827 {"BGEC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
829 {"BLTUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
831 {"BLTUC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
833 {"BGEUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
835 {"BGEUC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
837 {"BLTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
839 {"BLTZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
841 {"BLEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
843 {"BLEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
845 {"BGEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
847 {"BGEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
849 {"BGTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
851 {"BGTZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
853 {"BEQZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
855 {"BEQZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
857 {"BNEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
859 {"BNEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C, in GetOpcodeForInstruction()
861 {"BGEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZL rt,offset"}, in GetOpcodeForInstruction()
862 {"BGTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset"}, in GetOpcodeForInstruction()
863 {"BGTZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset"}, in GetOpcodeForInstruction()
864 {"BGTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZL rt,offset"}, in GetOpcodeForInstruction()
865 {"BLEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset"}, in GetOpcodeForInstruction()
866 {"BLEZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset"}, in GetOpcodeForInstruction()
867 {"BLEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZL rt,offset"}, in GetOpcodeForInstruction()
868 {"BLTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset"}, in GetOpcodeForInstruction()
869 {"BLTZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset"}, in GetOpcodeForInstruction()
870 {"BLTZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link, in GetOpcodeForInstruction()
872 {"BLTZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link, in GetOpcodeForInstruction()
874 {"BLTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZL rt,offset"}, in GetOpcodeForInstruction()
875 {"BOVC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
877 {"BNVC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C, in GetOpcodeForInstruction()
879 {"J", &EmulateInstructionMIPS64::Emulate_J, "J target"}, in GetOpcodeForInstruction()
880 {"JAL", &EmulateInstructionMIPS64::Emulate_JAL, "JAL target"}, in GetOpcodeForInstruction()
881 {"JALX", &EmulateInstructionMIPS64::Emulate_JAL, "JALX target"}, in GetOpcodeForInstruction()
882 {"JALR", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target"}, in GetOpcodeForInstruction()
883 {"JALR64", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target"}, in GetOpcodeForInstruction()
884 {"JALR_HB", &EmulateInstructionMIPS64::Emulate_JALR, "JALR.HB target"}, in GetOpcodeForInstruction()
885 {"JIALC", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset"}, in GetOpcodeForInstruction()
886 {"JIALC64", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset"}, in GetOpcodeForInstruction()
887 {"JIC", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset"}, in GetOpcodeForInstruction()
888 {"JIC64", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset"}, in GetOpcodeForInstruction()
889 {"JR", &EmulateInstructionMIPS64::Emulate_JR, "JR target"}, in GetOpcodeForInstruction()
890 {"JR64", &EmulateInstructionMIPS64::Emulate_JR, "JR target"}, in GetOpcodeForInstruction()
891 {"JR_HB", &EmulateInstructionMIPS64::Emulate_JR, "JR.HB target"}, in GetOpcodeForInstruction()
892 {"BC1F", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1F cc, offset"}, in GetOpcodeForInstruction()
893 {"BC1T", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1T cc, offset"}, in GetOpcodeForInstruction()
894 {"BC1FL", &EmulateInstructionMIPS64::Emulate_FP_branch, in GetOpcodeForInstruction()
896 {"BC1TL", &EmulateInstructionMIPS64::Emulate_FP_branch, in GetOpcodeForInstruction()
898 {"BC1EQZ", &EmulateInstructionMIPS64::Emulate_BC1EQZ, in GetOpcodeForInstruction()
900 {"BC1NEZ", &EmulateInstructionMIPS64::Emulate_BC1NEZ, in GetOpcodeForInstruction()
902 {"BC1ANY2F", &EmulateInstructionMIPS64::Emulate_3D_branch, in GetOpcodeForInstruction()
904 {"BC1ANY2T", &EmulateInstructionMIPS64::Emulate_3D_branch, in GetOpcodeForInstruction()
906 {"BC1ANY4F", &EmulateInstructionMIPS64::Emulate_3D_branch, in GetOpcodeForInstruction()
908 {"BC1ANY4T", &EmulateInstructionMIPS64::Emulate_3D_branch, in GetOpcodeForInstruction()
910 {"BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB, "BNZ.b wt,s16"}, in GetOpcodeForInstruction()
911 {"BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH, "BNZ.h wt,s16"}, in GetOpcodeForInstruction()
912 {"BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW, "BNZ.w wt,s16"}, in GetOpcodeForInstruction()
913 {"BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD, "BNZ.d wt,s16"}, in GetOpcodeForInstruction()
914 {"BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b wt,s16"}, in GetOpcodeForInstruction()
915 {"BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h wt,s16"}, in GetOpcodeForInstruction()
916 {"BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w wt,s16"}, in GetOpcodeForInstruction()
917 {"BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d wt,s16"}, in GetOpcodeForInstruction()
918 {"BNZ_V", &EmulateInstructionMIPS64::Emulate_BNZV, "BNZ.V wt,s16"}, in GetOpcodeForInstruction()
919 {"BZ_V", &EmulateInstructionMIPS64::Emulate_BZV, "BZ.V wt,s16"}, in GetOpcodeForInstruction()
929 bool EmulateInstructionMIPS64::ReadInstruction() { in ReadInstruction()
946 bool EmulateInstructionMIPS64::EvaluateInstruction(uint32_t evaluate_options) { in EvaluateInstruction()
1013 bool EmulateInstructionMIPS64::CreateFunctionEntryUnwind( in CreateFunctionEntryUnwind()
1040 bool EmulateInstructionMIPS64::nonvolatile_reg_p(uint64_t regnum) { in nonvolatile_reg_p()
1061 bool EmulateInstructionMIPS64::Emulate_DADDiu(llvm::MCInst &insn) { in Emulate_DADDiu()
1125 bool EmulateInstructionMIPS64::Emulate_SD(llvm::MCInst &insn) { in Emulate_SD()
1182 bool EmulateInstructionMIPS64::Emulate_LD(llvm::MCInst &insn) { in Emulate_LD()
1228 bool EmulateInstructionMIPS64::Emulate_LUI(llvm::MCInst &insn) { in Emulate_LUI()
1245 bool EmulateInstructionMIPS64::Emulate_DSUBU_DADDU(llvm::MCInst &insn) { in Emulate_DSUBU_DADDU()
1330 bool EmulateInstructionMIPS64::Emulate_BXX_3ops(llvm::MCInst &insn) { in Emulate_BXX_3ops()
1382 bool EmulateInstructionMIPS64::Emulate_Bcond_Link(llvm::MCInst &insn) { in Emulate_Bcond_Link()
1428 bool EmulateInstructionMIPS64::Emulate_BAL(llvm::MCInst &insn) { in Emulate_BAL()
1459 bool EmulateInstructionMIPS64::Emulate_BALC(llvm::MCInst &insn) { in Emulate_BALC()
1494 bool EmulateInstructionMIPS64::Emulate_Bcond_Link_C(llvm::MCInst &insn) { in Emulate_Bcond_Link_C()
1562 bool EmulateInstructionMIPS64::Emulate_BXX_2ops(llvm::MCInst &insn) { in Emulate_BXX_2ops()
1618 bool EmulateInstructionMIPS64::Emulate_BC(llvm::MCInst &insn) { in Emulate_BC()
1651 bool EmulateInstructionMIPS64::Emulate_BXX_3ops_C(llvm::MCInst &insn) { in Emulate_BXX_3ops_C()
1736 bool EmulateInstructionMIPS64::Emulate_BXX_2ops_C(llvm::MCInst &insn) { in Emulate_BXX_2ops_C()
1802 bool EmulateInstructionMIPS64::Emulate_J(llvm::MCInst &insn) { in Emulate_J()
1826 bool EmulateInstructionMIPS64::Emulate_JAL(llvm::MCInst &insn) { in Emulate_JAL()
1857 bool EmulateInstructionMIPS64::Emulate_JALR(llvm::MCInst &insn) { in Emulate_JALR()
1892 bool EmulateInstructionMIPS64::Emulate_JIALC(llvm::MCInst &insn) { in Emulate_JIALC()
1930 bool EmulateInstructionMIPS64::Emulate_JIC(llvm::MCInst &insn) { in Emulate_JIC()
1956 bool EmulateInstructionMIPS64::Emulate_JR(llvm::MCInst &insn) { in Emulate_JR()
1983 bool EmulateInstructionMIPS64::Emulate_FP_branch(llvm::MCInst &insn) { in Emulate_FP_branch()
2031 bool EmulateInstructionMIPS64::Emulate_BC1EQZ(llvm::MCInst &insn) { in Emulate_BC1EQZ()
2067 bool EmulateInstructionMIPS64::Emulate_BC1NEZ(llvm::MCInst &insn) { in Emulate_BC1NEZ()
2110 bool EmulateInstructionMIPS64::Emulate_3D_branch(llvm::MCInst &insn) { in Emulate_3D_branch()
2163 bool EmulateInstructionMIPS64::Emulate_BNZB(llvm::MCInst &insn) { in Emulate_BNZB()
2167 bool EmulateInstructionMIPS64::Emulate_BNZH(llvm::MCInst &insn) { in Emulate_BNZH()
2171 bool EmulateInstructionMIPS64::Emulate_BNZW(llvm::MCInst &insn) { in Emulate_BNZW()
2175 bool EmulateInstructionMIPS64::Emulate_BNZD(llvm::MCInst &insn) { in Emulate_BNZD()
2179 bool EmulateInstructionMIPS64::Emulate_BZB(llvm::MCInst &insn) { in Emulate_BZB()
2183 bool EmulateInstructionMIPS64::Emulate_BZH(llvm::MCInst &insn) { in Emulate_BZH()
2187 bool EmulateInstructionMIPS64::Emulate_BZW(llvm::MCInst &insn) { in Emulate_BZW()
2191 bool EmulateInstructionMIPS64::Emulate_BZD(llvm::MCInst &insn) { in Emulate_BZD()
2195 bool EmulateInstructionMIPS64::Emulate_MSA_Branch_DF(llvm::MCInst &insn, in Emulate_MSA_Branch_DF()
2255 bool EmulateInstructionMIPS64::Emulate_BNZV(llvm::MCInst &insn) { in Emulate_BNZV()
2259 bool EmulateInstructionMIPS64::Emulate_BZV(llvm::MCInst &insn) { in Emulate_BZV()
2263 bool EmulateInstructionMIPS64::Emulate_MSA_Branch_V(llvm::MCInst &insn, in Emulate_MSA_Branch_V()
2298 bool EmulateInstructionMIPS64::Emulate_LDST_Imm(llvm::MCInst &insn) { in Emulate_LDST_Imm()
2331 bool EmulateInstructionMIPS64::Emulate_LDST_Reg(llvm::MCInst &insn) { in Emulate_LDST_Reg()