43 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionMIPS, InstructionMIPS)  in LLDB_PLUGIN_DEFINE_ADV()  argument
62 EmulateInstructionMIPS::EmulateInstructionMIPS(  in EmulateInstructionMIPS()  function in EmulateInstructionMIPS
187 void EmulateInstructionMIPS::Initialize() {  in Initialize()
192 void EmulateInstructionMIPS::Terminate() {  in Terminate()
196 llvm::StringRef EmulateInstructionMIPS::GetPluginDescriptionStatic() {  in GetPluginDescriptionStatic()
201 EmulateInstructionMIPS::CreateInstance(const ArchSpec &arch,  in CreateInstance()
203   if (EmulateInstructionMIPS::SupportsEmulatingInstructionsOfTypeStatic(  in CreateInstance()
207       return new EmulateInstructionMIPS(arch);  in CreateInstance()
214 bool EmulateInstructionMIPS::SetTargetTriple(const ArchSpec &arch) {  in SetTargetTriple()
219 const char *EmulateInstructionMIPS::GetRegisterName(unsigned reg_num,  in GetRegisterName()
588 bool EmulateInstructionMIPS::GetRegisterInfo(RegisterKind reg_kind,  in GetRegisterInfo()
670 EmulateInstructionMIPS::MipsOpcode *
671 EmulateInstructionMIPS::GetOpcodeForInstruction(llvm::StringRef name) {  in GetOpcodeForInstruction()
672   static EmulateInstructionMIPS::MipsOpcode g_opcodes[] = {  in GetOpcodeForInstruction()
674       {"ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu,  in GetOpcodeForInstruction()
676       {"SW", &EmulateInstructionMIPS::Emulate_SW, "SW rt, offset(rs)"},  in GetOpcodeForInstruction()
677       {"LW", &EmulateInstructionMIPS::Emulate_LW, "LW rt, offset(base)"},  in GetOpcodeForInstruction()
678       {"SUBU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "SUBU rd, rs, rt"},  in GetOpcodeForInstruction()
679       {"ADDU", &EmulateInstructionMIPS::Emulate_SUBU_ADDU, "ADDU rd, rs, rt"},  in GetOpcodeForInstruction()
680       {"LUI", &EmulateInstructionMIPS::Emulate_LUI, "LUI rt, immediate"},  in GetOpcodeForInstruction()
683       {"ADDIUSP_MM", &EmulateInstructionMIPS::Emulate_ADDIUSP,  in GetOpcodeForInstruction()
685       {"ADDIUS5_MM", &EmulateInstructionMIPS::Emulate_ADDIUS5,  in GetOpcodeForInstruction()
687       {"SWSP_MM", &EmulateInstructionMIPS::Emulate_SWSP, "SWSP rt,offset(sp)"},  in GetOpcodeForInstruction()
688       {"SWM16_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,  in GetOpcodeForInstruction()
690       {"SWM32_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,  in GetOpcodeForInstruction()
692       {"SWP_MM", &EmulateInstructionMIPS::Emulate_SWM16_32,  in GetOpcodeForInstruction()
694       {"LWSP_MM", &EmulateInstructionMIPS::Emulate_LWSP, "LWSP rt,offset(sp)"},  in GetOpcodeForInstruction()
695       {"LWM16_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,  in GetOpcodeForInstruction()
697       {"LWM32_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,  in GetOpcodeForInstruction()
699       {"LWP_MM", &EmulateInstructionMIPS::Emulate_LWM16_32,  in GetOpcodeForInstruction()
701       {"JRADDIUSP", &EmulateInstructionMIPS::Emulate_JRADDIUSP,  in GetOpcodeForInstruction()
712       {"LB", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
714       {"LBE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
716       {"LBU", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
718       {"LBUE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
720       {"LDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
722       {"LD", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
724       {"LDL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
726       {"LDR", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
728       {"LLD", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
730       {"LDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
732       {"LDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
734       {"LH", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
736       {"LHE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
738       {"LHU", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
740       {"LHUE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
742       {"LL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
744       {"LLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
746       {"LUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
748       {"LW", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
750       {"LWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
752       {"LWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
754       {"LWE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
756       {"LWL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
758       {"LWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
760       {"LWR", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
762       {"LWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
764       {"LWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
766       {"LLX", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
768       {"LLXE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
770       {"LLDX", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
773       {"SB", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
775       {"SBE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
777       {"SC", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
779       {"SCE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
781       {"SCD", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
783       {"SD", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
785       {"SDL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
787       {"SDR", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
789       {"SDC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
791       {"SDC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
793       {"SDXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
795       {"SH", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
797       {"SHE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
799       {"SUXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
801       {"SWC1", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
803       {"SWC2", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
805       {"SWE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
807       {"SWL", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
809       {"SWLE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
811       {"SWR", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
813       {"SWRE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
815       {"SWXC1", &EmulateInstructionMIPS::Emulate_LDST_Reg,  in GetOpcodeForInstruction()
817       {"SCX", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
819       {"SCXE", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
821       {"SCDX", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
825       {"LBU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
827       {"LHU16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
829       {"LW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
831       {"LWGP_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
833       {"SH16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
835       {"SW16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
837       {"SW_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
839       {"SB16_MM", &EmulateInstructionMIPS::Emulate_LDST_Imm,  in GetOpcodeForInstruction()
843       {"BEQ", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BEQ rs,rt,offset"},  in GetOpcodeForInstruction()
844       {"BNE", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BNE rs,rt,offset"},  in GetOpcodeForInstruction()
845       {"BEQL", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BEQL rs,rt,offset"},  in GetOpcodeForInstruction()
846       {"BNEL", &EmulateInstructionMIPS::Emulate_BXX_3ops, "BNEL rs,rt,offset"},  in GetOpcodeForInstruction()
847       {"BGEZALL", &EmulateInstructionMIPS::Emulate_Bcond_Link,  in GetOpcodeForInstruction()
849       {"BAL", &EmulateInstructionMIPS::Emulate_BAL, "BAL offset"},  in GetOpcodeForInstruction()
850       {"BGEZAL", &EmulateInstructionMIPS::Emulate_Bcond_Link,  in GetOpcodeForInstruction()
852       {"BALC", &EmulateInstructionMIPS::Emulate_BALC, "BALC offset"},  in GetOpcodeForInstruction()
853       {"BC", &EmulateInstructionMIPS::Emulate_BC, "BC offset"},  in GetOpcodeForInstruction()
854       {"BGEZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGEZ rs,offset"},  in GetOpcodeForInstruction()
855       {"BLEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
857       {"BGEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
859       {"BLTZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
861       {"BGTZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
863       {"BEQZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
865       {"BNEZALC", &EmulateInstructionMIPS::Emulate_Bcond_Link_C,  in GetOpcodeForInstruction()
867       {"BEQC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
869       {"BNEC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
871       {"BLTC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
873       {"BGEC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
875       {"BLTUC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
877       {"BGEUC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
879       {"BLTZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BLTZC rt,offset"},  in GetOpcodeForInstruction()
880       {"BLEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BLEZC rt,offset"},  in GetOpcodeForInstruction()
881       {"BGEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BGEZC rt,offset"},  in GetOpcodeForInstruction()
882       {"BGTZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BGTZC rt,offset"},  in GetOpcodeForInstruction()
883       {"BEQZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BEQZC rt,offset"},  in GetOpcodeForInstruction()
884       {"BNEZC", &EmulateInstructionMIPS::Emulate_BXX_2ops_C, "BNEZC rt,offset"},  in GetOpcodeForInstruction()
885       {"BGEZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGEZL rt,offset"},  in GetOpcodeForInstruction()
886       {"BGTZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGTZ rt,offset"},  in GetOpcodeForInstruction()
887       {"BGTZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BGTZL rt,offset"},  in GetOpcodeForInstruction()
888       {"BLEZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLEZ rt,offset"},  in GetOpcodeForInstruction()
889       {"BLEZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLEZL rt,offset"},  in GetOpcodeForInstruction()
890       {"BLTZ", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLTZ rt,offset"},  in GetOpcodeForInstruction()
891       {"BLTZAL", &EmulateInstructionMIPS::Emulate_Bcond_Link,  in GetOpcodeForInstruction()
893       {"BLTZALL", &EmulateInstructionMIPS::Emulate_Bcond_Link,  in GetOpcodeForInstruction()
895       {"BLTZL", &EmulateInstructionMIPS::Emulate_BXX_2ops, "BLTZL rt,offset"},  in GetOpcodeForInstruction()
896       {"BOVC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
898       {"BNVC", &EmulateInstructionMIPS::Emulate_BXX_3ops_C,  in GetOpcodeForInstruction()
900       {"J", &EmulateInstructionMIPS::Emulate_J, "J target"},  in GetOpcodeForInstruction()
901       {"JAL", &EmulateInstructionMIPS::Emulate_JAL, "JAL target"},  in GetOpcodeForInstruction()
902       {"JALX", &EmulateInstructionMIPS::Emulate_JAL, "JALX target"},  in GetOpcodeForInstruction()
903       {"JALR", &EmulateInstructionMIPS::Emulate_JALR, "JALR target"},  in GetOpcodeForInstruction()
904       {"JALR_HB", &EmulateInstructionMIPS::Emulate_JALR, "JALR.HB target"},  in GetOpcodeForInstruction()
905       {"JIALC", &EmulateInstructionMIPS::Emulate_JIALC, "JIALC rt,offset"},  in GetOpcodeForInstruction()
906       {"JIC", &EmulateInstructionMIPS::Emulate_JIC, "JIC rt,offset"},  in GetOpcodeForInstruction()
907       {"JR", &EmulateInstructionMIPS::Emulate_JR, "JR target"},  in GetOpcodeForInstruction()
908       {"JR_HB", &EmulateInstructionMIPS::Emulate_JR, "JR.HB target"},  in GetOpcodeForInstruction()
909       {"BC1F", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1F cc, offset"},  in GetOpcodeForInstruction()
910       {"BC1T", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1T cc, offset"},  in GetOpcodeForInstruction()
911       {"BC1FL", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1FL cc, offset"},  in GetOpcodeForInstruction()
912       {"BC1TL", &EmulateInstructionMIPS::Emulate_FP_branch, "BC1TL cc, offset"},  in GetOpcodeForInstruction()
913       {"BC1EQZ", &EmulateInstructionMIPS::Emulate_BC1EQZ, "BC1EQZ ft, offset"},  in GetOpcodeForInstruction()
914       {"BC1NEZ", &EmulateInstructionMIPS::Emulate_BC1NEZ, "BC1NEZ ft, offset"},  in GetOpcodeForInstruction()
915       {"BC1ANY2F", &EmulateInstructionMIPS::Emulate_3D_branch,  in GetOpcodeForInstruction()
917       {"BC1ANY2T", &EmulateInstructionMIPS::Emulate_3D_branch,  in GetOpcodeForInstruction()
919       {"BC1ANY4F", &EmulateInstructionMIPS::Emulate_3D_branch,  in GetOpcodeForInstruction()
921       {"BC1ANY4T", &EmulateInstructionMIPS::Emulate_3D_branch,  in GetOpcodeForInstruction()
923       {"BNZ_B", &EmulateInstructionMIPS::Emulate_BNZB, "BNZ.b wt,s16"},  in GetOpcodeForInstruction()
924       {"BNZ_H", &EmulateInstructionMIPS::Emulate_BNZH, "BNZ.h wt,s16"},  in GetOpcodeForInstruction()
925       {"BNZ_W", &EmulateInstructionMIPS::Emulate_BNZW, "BNZ.w wt,s16"},  in GetOpcodeForInstruction()
926       {"BNZ_D", &EmulateInstructionMIPS::Emulate_BNZD, "BNZ.d wt,s16"},  in GetOpcodeForInstruction()
927       {"BZ_B", &EmulateInstructionMIPS::Emulate_BZB, "BZ.b wt,s16"},  in GetOpcodeForInstruction()
928       {"BZ_H", &EmulateInstructionMIPS::Emulate_BZH, "BZ.h wt,s16"},  in GetOpcodeForInstruction()
929       {"BZ_W", &EmulateInstructionMIPS::Emulate_BZW, "BZ.w wt,s16"},  in GetOpcodeForInstruction()
930       {"BZ_D", &EmulateInstructionMIPS::Emulate_BZD, "BZ.d wt,s16"},  in GetOpcodeForInstruction()
931       {"BNZ_V", &EmulateInstructionMIPS::Emulate_BNZV, "BNZ.V wt,s16"},  in GetOpcodeForInstruction()
932       {"BZ_V", &EmulateInstructionMIPS::Emulate_BZV, "BZ.V wt,s16"},  in GetOpcodeForInstruction()
935       {"B16_MM", &EmulateInstructionMIPS::Emulate_B16_MM, "B16 offset"},  in GetOpcodeForInstruction()
936       {"BEQZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
938       {"BNEZ16_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
940       {"BEQZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
942       {"BNEZC_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
944       {"BGEZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
946       {"BLTZALS_MM", &EmulateInstructionMIPS::Emulate_Branch_MM,  in GetOpcodeForInstruction()
948       {"JALR16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALR16 rs"},  in GetOpcodeForInstruction()
949       {"JALRS16_MM", &EmulateInstructionMIPS::Emulate_JALRx16_MM, "JALRS16 rs"},  in GetOpcodeForInstruction()
950       {"JR16_MM", &EmulateInstructionMIPS::Emulate_JR, "JR16 rs rs"},  in GetOpcodeForInstruction()
951       {"JRC16_MM", &EmulateInstructionMIPS::Emulate_JR, "JRC16 rs rs"},  in GetOpcodeForInstruction()
952       {"JALS_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALS target"},  in GetOpcodeForInstruction()
953       {"JALX_MM", &EmulateInstructionMIPS::Emulate_JALx, "JALX target"},  in GetOpcodeForInstruction()
954       {"JALRS_MM", &EmulateInstructionMIPS::Emulate_JALRS, "JALRS rt, rs"},  in GetOpcodeForInstruction()
965 EmulateInstructionMIPS::GetSizeOfInstruction(lldb_private::DataExtractor &data,  in GetSizeOfInstruction()
985 bool EmulateInstructionMIPS::SetInstruction(const Opcode &insn_opcode,  in SetInstruction()
1032 bool EmulateInstructionMIPS::ReadInstruction() {  in ReadInstruction()
1049 bool EmulateInstructionMIPS::EvaluateInstruction(uint32_t evaluate_options) {  in EvaluateInstruction()
1124 bool EmulateInstructionMIPS::CreateFunctionEntryUnwind(  in CreateFunctionEntryUnwind()
1150 bool EmulateInstructionMIPS::nonvolatile_reg_p(uint32_t regnum) {  in nonvolatile_reg_p()
1171 bool EmulateInstructionMIPS::Emulate_ADDiu(llvm::MCInst &insn) {  in Emulate_ADDiu()
1223 bool EmulateInstructionMIPS::Emulate_SW(llvm::MCInst &insn) {  in Emulate_SW()
1287 bool EmulateInstructionMIPS::Emulate_LW(llvm::MCInst &insn) {  in Emulate_LW()
1334 bool EmulateInstructionMIPS::Emulate_SUBU_ADDU(llvm::MCInst &insn) {  in Emulate_SUBU_ADDU()
1412 bool EmulateInstructionMIPS::Emulate_LUI(llvm::MCInst &insn) {  in Emulate_LUI()
1429 bool EmulateInstructionMIPS::Emulate_ADDIUSP(llvm::MCInst &insn) {  in Emulate_ADDIUSP()
1455 bool EmulateInstructionMIPS::Emulate_ADDIUS5(llvm::MCInst &insn) {  in Emulate_ADDIUS5()
1488 bool EmulateInstructionMIPS::Emulate_SWSP(llvm::MCInst &insn) {  in Emulate_SWSP()
1553 bool EmulateInstructionMIPS::Emulate_SWM16_32(llvm::MCInst &insn) {  in Emulate_SWM16_32()
1630 bool EmulateInstructionMIPS::Emulate_LWSP(llvm::MCInst &insn) {  in Emulate_LWSP()
1681 bool EmulateInstructionMIPS::Emulate_LWM16_32(llvm::MCInst &insn) {  in Emulate_LWM16_32()
1738 bool EmulateInstructionMIPS::Emulate_JRADDIUSP(llvm::MCInst &insn) {  in Emulate_JRADDIUSP()
1790 bool EmulateInstructionMIPS::Emulate_BXX_3ops(llvm::MCInst &insn) {  in Emulate_BXX_3ops()
1840 bool EmulateInstructionMIPS::Emulate_BXX_3ops_C(llvm::MCInst &insn) {  in Emulate_BXX_3ops_C()
1919 bool EmulateInstructionMIPS::Emulate_Bcond_Link_C(llvm::MCInst &insn) {  in Emulate_Bcond_Link_C()
1988 bool EmulateInstructionMIPS::Emulate_Bcond_Link(llvm::MCInst &insn) {  in Emulate_Bcond_Link()
2039 bool EmulateInstructionMIPS::Emulate_BXX_2ops(llvm::MCInst &insn) {  in Emulate_BXX_2ops()
2096 bool EmulateInstructionMIPS::Emulate_BXX_2ops_C(llvm::MCInst &insn) {  in Emulate_BXX_2ops_C()
2156 bool EmulateInstructionMIPS::Emulate_B16_MM(llvm::MCInst &insn) {  in Emulate_B16_MM()
2183 bool EmulateInstructionMIPS::Emulate_Branch_MM(llvm::MCInst &insn) {  in Emulate_Branch_MM()
2284 bool EmulateInstructionMIPS::Emulate_JALRx16_MM(llvm::MCInst &insn) {  in Emulate_JALRx16_MM()
2323 bool EmulateInstructionMIPS::Emulate_JALx(llvm::MCInst &insn) {  in Emulate_JALx()
2368 bool EmulateInstructionMIPS::Emulate_JALRS(llvm::MCInst &insn) {  in Emulate_JALRS()
2405 bool EmulateInstructionMIPS::Emulate_BAL(llvm::MCInst &insn) {  in Emulate_BAL()
2436 bool EmulateInstructionMIPS::Emulate_BALC(llvm::MCInst &insn) {  in Emulate_BALC()
2467 bool EmulateInstructionMIPS::Emulate_BC(llvm::MCInst &insn) {  in Emulate_BC()
2490 bool EmulateInstructionMIPS::Emulate_J(llvm::MCInst &insn) {  in Emulate_J()
2513 bool EmulateInstructionMIPS::Emulate_JAL(llvm::MCInst &insn) {  in Emulate_JAL()
2544 bool EmulateInstructionMIPS::Emulate_JALR(llvm::MCInst &insn) {  in Emulate_JALR()
2579 bool EmulateInstructionMIPS::Emulate_JIALC(llvm::MCInst &insn) {  in Emulate_JIALC()
2617 bool EmulateInstructionMIPS::Emulate_JIC(llvm::MCInst &insn) {  in Emulate_JIC()
2643 bool EmulateInstructionMIPS::Emulate_JR(llvm::MCInst &insn) {  in Emulate_JR()
2670 bool EmulateInstructionMIPS::Emulate_FP_branch(llvm::MCInst &insn) {  in Emulate_FP_branch()
2709 bool EmulateInstructionMIPS::Emulate_BC1EQZ(llvm::MCInst &insn) {  in Emulate_BC1EQZ()
2745 bool EmulateInstructionMIPS::Emulate_BC1NEZ(llvm::MCInst &insn) {  in Emulate_BC1NEZ()
2788 bool EmulateInstructionMIPS::Emulate_3D_branch(llvm::MCInst &insn) {  in Emulate_3D_branch()
2840 bool EmulateInstructionMIPS::Emulate_BNZB(llvm::MCInst &insn) {  in Emulate_BNZB()
2844 bool EmulateInstructionMIPS::Emulate_BNZH(llvm::MCInst &insn) {  in Emulate_BNZH()
2848 bool EmulateInstructionMIPS::Emulate_BNZW(llvm::MCInst &insn) {  in Emulate_BNZW()
2852 bool EmulateInstructionMIPS::Emulate_BNZD(llvm::MCInst &insn) {  in Emulate_BNZD()
2856 bool EmulateInstructionMIPS::Emulate_BZB(llvm::MCInst &insn) {  in Emulate_BZB()
2860 bool EmulateInstructionMIPS::Emulate_BZH(llvm::MCInst &insn) {  in Emulate_BZH()
2864 bool EmulateInstructionMIPS::Emulate_BZW(llvm::MCInst &insn) {  in Emulate_BZW()
2868 bool EmulateInstructionMIPS::Emulate_BZD(llvm::MCInst &insn) {  in Emulate_BZD()
2872 bool EmulateInstructionMIPS::Emulate_MSA_Branch_DF(llvm::MCInst &insn,  in Emulate_MSA_Branch_DF()
2932 bool EmulateInstructionMIPS::Emulate_BNZV(llvm::MCInst &insn) {  in Emulate_BNZV()
2936 bool EmulateInstructionMIPS::Emulate_BZV(llvm::MCInst &insn) {  in Emulate_BZV()
2940 bool EmulateInstructionMIPS::Emulate_MSA_Branch_V(llvm::MCInst &insn,  in Emulate_MSA_Branch_V()
2975 bool EmulateInstructionMIPS::Emulate_LDST_Imm(llvm::MCInst &insn) {  in Emulate_LDST_Imm()
3008 bool EmulateInstructionMIPS::Emulate_LDST_Reg(llvm::MCInst &insn) {  in Emulate_LDST_Reg()