9 signed int si;  variable
22   (void) __sync_fetch_and_add (&si, 1); // CHECK: atomicrmw add i32* {{.*}} seq_cst, align 4  in test_op_ignore()
31   (void) __sync_fetch_and_sub (&si, 1); // CHECK: atomicrmw sub i32* {{.*}} seq_cst, align 4  in test_op_ignore()
40   (void) __sync_fetch_and_or (&si, 1); // CHECK: atomicrmw or i32* {{.*}} seq_cst, align 4  in test_op_ignore()
49   (void) __sync_fetch_and_xor (&si, 1); // CHECK: atomicrmw xor i32* {{.*}} seq_cst, align 4  in test_op_ignore()
60   (void) __sync_fetch_and_nand (&si, 1); // CHECK: atomicrmw nand i32* {{.*}} seq_cst, align 4  in test_op_ignore()
69   (void) __sync_fetch_and_and (&si, 1); // CHECK: atomicrmw and i32* {{.*}} seq_cst, align 4  in test_op_ignore()
82   si = __sync_fetch_and_add (&si, 11); // CHECK: atomicrmw add  in test_fetch_and_op()
91   si = __sync_fetch_and_sub (&si, 11); // CHECK: atomicrmw sub  in test_fetch_and_op()
100   si = __sync_fetch_and_or (&si, 11); // CHECK: atomicrmw or  in test_fetch_and_op()
109   si = __sync_fetch_and_xor (&si, 11); // CHECK: atomicrmw xor  in test_fetch_and_op()
118   si = __sync_fetch_and_nand (&si, 11); // CHECK: atomicrmw nand  in test_fetch_and_op()
127   si = __sync_fetch_and_and (&si, 11); // CHECK: atomicrmw and  in test_fetch_and_op()
140   si = __sync_add_and_fetch (&si, uc); // CHECK: atomicrmw add  in test_op_and_fetch()
149   si = __sync_sub_and_fetch (&si, uc); // CHECK: atomicrmw sub  in test_op_and_fetch()
158   si = __sync_or_and_fetch (&si, uc); // CHECK: atomicrmw or  in test_op_and_fetch()
167   si = __sync_xor_and_fetch (&si, uc); // CHECK: atomicrmw xor  in test_op_and_fetch()
188   si = __sync_nand_and_fetch (&si, uc); // CHECK: atomicrmw nand  in test_op_and_fetch()
217   si = __sync_and_and_fetch (&si, uc); // CHECK: atomicrmw and  in test_op_and_fetch()
242   si = __sync_val_compare_and_swap (&si, uc, sc);  in test_compare_and_swap()
275   ui = __sync_bool_compare_and_swap (&si, uc, sc);  in test_compare_and_swap()
298   si = __sync_lock_test_and_set (&si, 1); // CHECK: atomicrmw xchg i32* {{.*}} seq_cst, align 4  in test_lock()
309   __sync_lock_release (&si); // CHECK: store atomic {{.*}} release, align 4  in test_lock()
317   si = __atomic_fetch_min(&si, 5, __ATOMIC_SEQ_CST); // CHECK: atomicrmw min {{.*}} seq_cst, align 4  in test_atomic()
319   si = __atomic_fetch_max(&si, 5, __ATOMIC_RELEASE); // CHECK: atomicrmw max {{.*}} release, align 4  in test_atomic()