Lines Matching refs:IVSigned

2757   const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation();  in EmitOMPOuterLoop()  local
2781 RT.emitForNext(*this, S.getBeginLoc(), IVSize, IVSigned, LoopArgs.IL, in EmitOMPOuterLoop()
2822 [&S, &LoopArgs, LoopExit, &CodeGenLoop, IVSize, IVSigned, &CodeGenOrdered, in EmitOMPOuterLoop()
2835 [IVSize, IVSigned, Loc, &CodeGenOrdered](CodeGenFunction &CGF) { in EmitOMPOuterLoop()
2836 CodeGenOrdered(CGF, Loc, IVSize, IVSigned); in EmitOMPOuterLoop()
2929 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPForOuterLoop() local
2939 IVSigned, Ordered, DipatchRTInputValues); in EmitOMPForOuterLoop()
2942 IVSize, IVSigned, Ordered, LoopArgs.IL, LoopArgs.LB, LoopArgs.UB, in EmitOMPForOuterLoop()
2950 const bool IVSigned) { in EmitOMPForOuterLoop() argument
2953 IVSigned); in EmitOMPForOuterLoop()
2969 const unsigned IVSize, const bool IVSigned) {} in emitEmptyOrdered() argument
2985 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeOuterLoop() local
2988 IVSize, IVSigned, /* Ordered = */ false, LoopArgs.IL, LoopArgs.LB, in EmitOMPDistributeOuterLoop()
3317 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPWorksharingLoop() local
3350 [IVSize, IVSigned, Ordered, IL, LB, UB, ST, StaticChunkedOne, Chunk, in EmitOMPWorksharingLoop()
3359 IVSize, IVSigned, Ordered, IL.getAddress(CGF), in EmitOMPWorksharingLoop()
5598 const bool IVSigned = IVExpr->getType()->hasSignedIntegerRepresentation(); in EmitOMPDistributeLoop() local
5615 IVSize, IVSigned, /* Ordered = */ false, IL.getAddress(*this), in EmitOMPDistributeLoop()