Lines Matching refs:OutputBecomesInput
11606 bool OutputBecomesInput = false; in getNDSWDS() local
11612 OutputBecomesInput = true; in getNDSWDS()
11631 OutputBecomesInput); in getNDSWDS()
11640 StringRef MangledName, bool OutputBecomesInput, in addAArch64VectorName() argument
11645 if (OutputBecomesInput) in addAArch64VectorName()
11656 bool OutputBecomesInput, in addAArch64AdvSIMDNDSNames() argument
11661 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11663 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11667 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11669 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11673 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11675 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11680 OutputBecomesInput, Fn); in addAArch64AdvSIMDNDSNames()
11698 const bool OutputBecomesInput = std::get<2>(Data); in emitAArch64DeclareSimdFunction() local
11742 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11750 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11752 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11756 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11760 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11770 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11779 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11781 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11785 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()
11789 OutputBecomesInput, Fn); in emitAArch64DeclareSimdFunction()