21 …"Description": "Intel(R) Optane(TM) Persistent Memory(PMEM)  bandwidth total includes Intel(R) Opt…  string
44 …"Description": "DDR memory bandwidth total includes DDR memory read bandwidth and DDR memory write…  string
67 …"Description": "Total memory read accesses includes memory reads from last level cache (LLC) addre…  string
86             "Description": "",  string
101             "Description": "Ratio values should be within value range [0,1)",  string
148             "Description": "Sum of TMA level 1 metrics should be 100%",  string
175             "Description": "Sum of the level 2 children should equal level 1 parent",  string
198             "Description": "Sum of the level 2 children should equal level 1 parent",  string
221             "Description": "Sum of the level 2 children should equal level 1 parent",  string
244             "Description": "Sum of the level 2 children should equal level 1 parent",  string
267 …"Description": "The all_requests includes the memory_page_empty, memory_page_misses, and memory_pa…  string
290             "Description": "CPU utilization in kernel mode should always be <= cpu utilization",  string
309 …"Description": "Total L2 misses per instruction should be >= L2 demand data read misses per instru…  string
328 …"Description": "Total L2 misses per instruction should be >= L2 demand code misses per instruction…  string
347 …"Description": "L3 data read, rfo, code misses per instruction equals total L3 misses per instruct…  string
374             "Description": "Setting generous range for allowable frequencies",  string
389             "Description": "Setting generous range for allowable frequencies",  string