Lines Matching refs:V4L2_HEVC_DPB_ENTRIES_NUM_MAX
2303 #define V4L2_HEVC_DPB_ENTRIES_NUM_MAX 16 macro
2348 __s8 delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2349 __s8 luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2350 __s8 delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
2351 __s8 chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
2353 __s8 delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2354 __s8 luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2355 __s8 delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
2356 __s8 chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
2456 __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2457 __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2506 __u8 poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2507 __u8 poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2508 __u8 poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
2511 struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];