Lines Matching refs:__u32
52 __u32 major_version; /* from KFD */
53 __u32 minor_version; /* from KFD */
74 __u32 ring_size; /* to KFD */
75 __u32 gpu_id; /* to KFD */
76 __u32 queue_type; /* to KFD */
77 __u32 queue_percentage; /* to KFD */
78 __u32 queue_priority; /* to KFD */
79 __u32 queue_id; /* from KFD */
84 __u32 ctx_save_restore_size; /* to KFD */
85 __u32 ctl_stack_size; /* to KFD */
86 __u32 sdma_engine_id; /* to KFD */
87 __u32 pad;
91 __u32 queue_id; /* to KFD */
92 __u32 pad;
98 __u32 queue_id; /* to KFD */
99 __u32 ring_size; /* to KFD */
100 __u32 queue_percentage; /* to KFD */
101 __u32 queue_priority; /* to KFD */
105 __u32 queue_id; /* to KFD */
106 __u32 num_cu_mask; /* to KFD */
112 __u32 ctl_stack_used_size; /* from KFD */
113 __u32 save_area_used_size; /* from KFD */
114 __u32 queue_id; /* to KFD */
115 __u32 pad;
120 __u32 gpu_id; /* to KFD */
121 __u32 pad;
132 __u32 gpu_id;
133 __u32 location_id;
134 __u32 vendor_id;
135 __u32 device_id;
136 __u32 revision_id;
137 __u32 subsystem_vendor_id;
138 __u32 subsystem_device_id;
139 __u32 fw_version;
140 __u32 gfx_target_version;
141 __u32 simd_count;
142 __u32 max_waves_per_simd;
143 __u32 array_count;
144 __u32 simd_arrays_per_engine;
145 __u32 num_xcc;
146 __u32 capability;
147 __u32 debug_prop;
161 __u32 gpu_id; /* to KFD */
162 __u32 default_policy; /* to KFD */
163 __u32 alternate_policy; /* to KFD */
164 __u32 misc_process_flag; /* to KFD */
180 __u32 gpu_id; /* to KFD */
181 __u32 pad;
191 __u32 gpu_id; /* from KFD */
192 __u32 pad;
206 __u32 num_of_nodes;
207 __u32 pad;
219 __u32 num_of_nodes;
220 __u32 pad;
228 __u32 gpu_id; /* to KFD */
229 __u32 pad;
233 __u32 gpu_id; /* to KFD */
234 __u32 pad;
239 __u32 gpu_id; /* to KFD */
240 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */
245 __u32 gpu_id; /* to KFD */
246 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */
284 __u32 event_trigger_data; /* from KFD - signal events only */
285 __u32 event_type; /* to KFD */
286 __u32 auto_reset; /* to KFD */
287 __u32 node_id; /* to KFD - only valid for certain
289 __u32 event_id; /* from KFD */
290 __u32 event_slot_index; /* from KFD */
294 __u32 event_id; /* to KFD */
295 __u32 pad;
299 __u32 event_id; /* to KFD */
300 __u32 pad;
304 __u32 event_id; /* to KFD */
305 __u32 pad;
309 __u32 NotPresent; /* Page not present or supervisor privilege */
310 __u32 ReadOnly; /* Write access to a read-only page */
311 __u32 NoExecute; /* Execute access to a page marked NX */
312 __u32 imprecise; /* Can't determine the exact fault address */
319 __u32 gpu_id;
320 __u32 ErrorType; /* 0 = no RAS error,
330 __u32 reset_type;
331 __u32 reset_cause;
332 __u32 memory_lost;
333 __u32 gpu_id;
352 __u32 event_id; /* to KFD */
353 __u32 pad;
359 __u32 num_events; /* to KFD */
360 __u32 wait_for_all; /* to KFD */
361 __u32 timeout; /* to KFD */
362 __u32 wait_result; /* from KFD */
367 __u32 gpu_id; /* to KFD */
368 __u32 pad;
379 __u32 num_tile_configs;
383 __u32 num_macro_tile_configs;
385 __u32 gpu_id; /* to KFD */
386 __u32 gb_addr_config; /* from KFD */
387 __u32 num_banks; /* from KFD */
388 __u32 num_ranks; /* from KFD */
397 __u32 gpu_id; /* to KFD */
398 __u32 pad;
402 __u32 drm_fd; /* to KFD */
403 __u32 gpu_id; /* to KFD */
440 __u32 gpu_id; /* to KFD */
441 __u32 flags;
470 __u32 n_devices; /* to KFD */
471 __u32 n_success; /* to/from KFD */
481 __u32 n_devices; /* to KFD */
482 __u32 n_success; /* to/from KFD */
493 __u32 queue_id; /* to KFD */
494 __u32 num_gws; /* to KFD */
495 __u32 first_gws; /* from KFD */
496 __u32 pad;
502 __u32 metadata_size; /* to KFD (space allocated by user)
505 __u32 gpu_id; /* from KFD */
506 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
507 __u32 dmabuf_fd; /* to KFD */
513 __u32 gpu_id; /* to KFD */
514 __u32 dmabuf_fd; /* to KFD */
519 __u32 flags; /* to KFD */
520 __u32 dmabuf_fd; /* from KFD */
578 __u32 gpuid; /* to KFD */
579 __u32 anon_fd; /* from KFD */
702 __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */
703 __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */
704 __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */
705 __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */
706 __u32 op;
710 __u32 user_gpu_id;
711 __u32 actual_gpu_id;
712 __u32 drm_fd;
713 __u32 pad;
721 __u32 gpu_id; /* This is the user_gpu_id */
722 __u32 alloc_flags;
723 __u32 dmabuf_fd;
724 __u32 pad;
814 __u32 type;
815 __u32 value;
859 __u32 op;
860 __u32 nattr;
1036 __u32 runtime_state;
1037 __u32 ttmp_setup;
1065 __u32 mode_mask;
1066 __u32 capabilities_mask;
1076 __u32 queue_id;
1077 __u32 gpu_id;
1078 __u32 ring_size;
1079 __u32 queue_type;
1080 __u32 ctx_save_restore_area_size;
1081 __u32 reserved;
1093 __u32 control_stack_offset;
1094 __u32 control_stack_size;
1095 __u32 wave_state_offset;
1096 __u32 wave_state_size;
1098 __u32 debug_offset;
1099 __u32 debug_size;
1101 __u32 err_event_id;
1102 __u32 reserved1;
1173 __u32 rinfo_size;
1174 __u32 dbg_fd;
1198 __u32 gpu_id;
1199 __u32 queue_id;
1241 __u32 override_mode;
1242 __u32 enable_mask;
1243 __u32 support_request_mask;
1244 __u32 pad;
1259 __u32 launch_mode;
1260 __u32 pad;
1296 __u32 num_queues;
1297 __u32 grace_period;
1320 __u32 num_queues;
1321 __u32 pad;
1344 __u32 mode;
1345 __u32 mask;
1346 __u32 gpu_id;
1347 __u32 id;
1365 __u32 gpu_id;
1366 __u32 id;
1382 __u32 flags;
1383 __u32 pad;
1411 __u32 gpu_id;
1412 __u32 queue_id;
1438 __u32 info_size;
1439 __u32 source_id;
1440 __u32 exception_code;
1441 __u32 clear_exception;
1476 __u32 num_queues;
1477 __u32 entry_size;
1512 __u32 num_devices;
1513 __u32 entry_size;
1528 __u32 pid;
1529 __u32 op;