Lines Matching defs:mlx5_ifc_mtpps_reg_bits
11181 struct mlx5_ifc_mtpps_reg_bits { struct
11182 u8 reserved_at_0[0xc];
11183 u8 cap_number_of_pps_pins[0x4];
11184 u8 reserved_at_10[0x4];
11185 u8 cap_max_num_of_pps_in_pins[0x4];
11186 u8 reserved_at_18[0x4];
11187 u8 cap_max_num_of_pps_out_pins[0x4];
11189 u8 reserved_at_20[0x13];
11190 u8 cap_log_min_npps_period[0x5];
11191 u8 reserved_at_38[0x3];
11192 u8 cap_log_min_out_pulse_duration_ns[0x5];
11194 u8 reserved_at_40[0x4];
11195 u8 cap_pin_3_mode[0x4];
11196 u8 reserved_at_48[0x4];
11197 u8 cap_pin_2_mode[0x4];
11198 u8 reserved_at_50[0x4];
11199 u8 cap_pin_1_mode[0x4];
11200 u8 reserved_at_58[0x4];
11201 u8 cap_pin_0_mode[0x4];
11203 u8 reserved_at_60[0x4];
11204 u8 cap_pin_7_mode[0x4];
11205 u8 reserved_at_68[0x4];
11206 u8 cap_pin_6_mode[0x4];
11207 u8 reserved_at_70[0x4];
11208 u8 cap_pin_5_mode[0x4];
11209 u8 reserved_at_78[0x4];
11210 u8 cap_pin_4_mode[0x4];
11212 u8 field_select[0x20];
11213 u8 reserved_at_a0[0x20];
11215 u8 npps_period[0x40];
11217 u8 enable[0x1];
11218 u8 reserved_at_101[0xb];
11219 u8 pattern[0x4];
11220 u8 reserved_at_110[0x4];
11221 u8 pin_mode[0x4];
11222 u8 pin[0x8];
11224 u8 reserved_at_120[0x2];
11225 u8 out_pulse_duration_ns[0x1e];
11227 u8 time_stamp[0x40];
11229 u8 out_pulse_duration[0x10];
11230 u8 out_periodic_adjustment[0x10];
11231 u8 enhanced_out_periodic_adjustment[0x20];
11233 u8 reserved_at_1c0[0x20];