Lines Matching refs:MLX5_GET
96 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ macro
101 u32 ___t = MLX5_GET(typ, p, fld); \
150 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
153 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
156 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
1288 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1294 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1297 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1303 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1306 MLX5_GET(per_protocol_networking_offload_caps,\
1310 MLX5_GET(per_protocol_networking_offload_caps,\
1314 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1317 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1320 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1323 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1326 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1356 MLX5_GET(flow_table_eswitch_cap, \
1375 MLX5_GET(e_switch_cap, \
1383 MLX5_GET(port_selection_cap, \
1387 MLX5_GET(port_selection_cap, \
1391 MLX5_GET(adv_virtualization_cap, \
1395 MLX5_GET(adv_rdma_cap, \
1405 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1408 (MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1410 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1412 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1416 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1419 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1422 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1425 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1428 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1431 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1435 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1439 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \
1443 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1446 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1449 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1452 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1458 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1464 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1470 MLX5_GET(virtio_emulation_cap, \
1478 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1481 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1484 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1487 MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)