21 		dev_err(dev, "%s: unable to soft-reset Cadence IP: %d\n", __func__, ret);  in intel_start_bus()
34 		dev_err(dev, "%s: unable to initialize Cadence IP: %d\n", __func__, ret);  in intel_start_bus()
43 			dev_err(dev, "%s: sync go failed: %d\n", __func__, ret);  in intel_start_bus()
50 		dev_err(dev, "%s: CONFIG_UPDATE BIT still set\n", __func__);  in intel_start_bus()
56 		dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret);  in intel_start_bus()
62 		dev_err(dev, "%s: unable to exit bus reset sequence: %d\n", __func__, ret);  in intel_start_bus()
118 			dev_err(dev, "cannot enable interrupts during resume\n");  in intel_start_bus_after_reset()
125 		dev_err(dev, "unable to restart clock during resume\n");  in intel_start_bus_after_reset()
137 				dev_err(sdw->cdns.dev, "sync go failed during resume\n");  in intel_start_bus_after_reset()
144 			dev_err(dev, "%s: CONFIG_UPDATE BIT still set\n", __func__);  in intel_start_bus_after_reset()
150 			dev_err(dev, "cannot enable interrupts during resume\n");  in intel_start_bus_after_reset()
156 			dev_err(dev, "unable to exit bus reset sequence during resume\n");  in intel_start_bus_after_reset()
176 		dev_err(dev, "%s: invalid configuration, clock was not stopped\n", __func__);  in intel_check_clock_stop()
187 		dev_err(dev, "%s: unable to restart clock: %d\n", __func__, ret);  in intel_start_bus_after_clock_stop()
193 		dev_err(dev, "%s: cannot enable interrupts: %d\n", __func__, ret);  in intel_start_bus_after_clock_stop()
217 			dev_err(dev, "%s: cannot stop clock: %d\n", __func__, ret);  in intel_stop_bus()
224 		dev_err(dev, "%s: cannot disable interrupts: %d\n", __func__, ret);  in intel_stop_bus()
230 		dev_err(dev, "%s: Link power down failed: %d\n", __func__, ret);  in intel_stop_bus()
283 		dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);  in intel_post_bank_switch()