63 	u32 ctrl;  in mpfs_rtc_start()  local
65 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_start()
66 	ctrl &= ~CONTROL_STOP_BIT;  in mpfs_rtc_start()
67 	ctrl |= CONTROL_START_BIT;  in mpfs_rtc_start()
68 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_start()
101 	u32 ctrl, prog;  in mpfs_rtc_settime()  local
110 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_settime()
111 	ctrl &= ~CONTROL_STOP_BIT;  in mpfs_rtc_settime()
112 	ctrl |= CONTROL_UPLOAD_BIT;  in mpfs_rtc_settime()
113 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_settime()
144 	u32 mode, ctrl;  in mpfs_rtc_setalarm()  local
148 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_setalarm()
149 	ctrl |= CONTROL_ALARM_OFF_BIT;  in mpfs_rtc_setalarm()
150 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_setalarm()
162 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_setalarm()
167 		ctrl &= ~CONTROL_ALARM_OFF_BIT;  in mpfs_rtc_setalarm()
168 		ctrl |= CONTROL_ALARM_ON_BIT;  in mpfs_rtc_setalarm()
170 	ctrl &= ~CONTROL_STOP_BIT;  in mpfs_rtc_setalarm()
171 	ctrl |= CONTROL_START_BIT;  in mpfs_rtc_setalarm()
172 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_setalarm()
181 	u32 ctrl;  in mpfs_rtc_alarm_irq_enable()  local
183 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_alarm_irq_enable()
184 	ctrl &= ~(CONTROL_ALARM_ON_BIT | CONTROL_ALARM_OFF_BIT | CONTROL_STOP_BIT);  in mpfs_rtc_alarm_irq_enable()
187 		ctrl |= CONTROL_ALARM_ON_BIT;  in mpfs_rtc_alarm_irq_enable()
189 		ctrl |= CONTROL_ALARM_OFF_BIT;  in mpfs_rtc_alarm_irq_enable()
191 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_alarm_irq_enable()