Lines Matching refs:pin_reg
43 u32 pin_reg; in amd_gpio_get_direction() local
47 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
50 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) in amd_gpio_get_direction()
59 u32 pin_reg; in amd_gpio_direction_input() local
63 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
64 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()
65 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
74 u32 pin_reg; in amd_gpio_direction_output() local
79 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
80 pin_reg |= BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_output()
82 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
84 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
85 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
93 u32 pin_reg; in amd_gpio_get_value() local
98 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
101 return !!(pin_reg & BIT(PIN_STS_OFF)); in amd_gpio_get_value()
106 u32 pin_reg; in amd_gpio_set_value() local
111 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
113 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
115 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
116 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
124 u32 pin_reg; in amd_gpio_set_debounce() local
129 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_set_debounce()
130 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) in amd_gpio_set_debounce()
134 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
137 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_set_debounce()
138 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
150 pin_reg |= 1; in amd_gpio_set_debounce()
151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
155 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
160 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
161 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
162 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
165 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
166 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
167 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
170 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
171 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
172 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
174 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_set_debounce()
178 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
179 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
180 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
181 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_set_debounce()
183 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
191 u32 pin_reg; in amd_gpio_dbg_show() local
245 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
248 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { in amd_gpio_dbg_show()
249 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & in amd_gpio_dbg_show()
256 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && in amd_gpio_dbg_show()
262 if (pin_reg & BIT(LEVEL_TRIG_OFF)) in amd_gpio_dbg_show()
267 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) in amd_gpio_dbg_show()
272 if (pin_reg & BIT(INTERRUPT_STS_OFF)) in amd_gpio_dbg_show()
285 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) in amd_gpio_dbg_show()
291 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) in amd_gpio_dbg_show()
297 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) in amd_gpio_dbg_show()
303 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) in amd_gpio_dbg_show()
309 if (pin_reg & BIT(WAKE_STS_OFF)) in amd_gpio_dbg_show()
315 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { in amd_gpio_dbg_show()
317 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { in amd_gpio_dbg_show()
323 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { in amd_gpio_dbg_show()
325 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) in amd_gpio_dbg_show()
331 if (pin_reg & BIT(PIN_STS_OFF)) in amd_gpio_dbg_show()
338 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; in amd_gpio_dbg_show()
340 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_dbg_show()
341 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); in amd_gpio_dbg_show()
342 time = pin_reg & DB_TMR_OUT_MASK; in amd_gpio_dbg_show()
365 seq_printf(s, "0x%x\n", pin_reg); in amd_gpio_dbg_show()
375 u32 pin_reg; in amd_gpio_irq_enable() local
383 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
384 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_enable()
385 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_enable()
386 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
392 u32 pin_reg; in amd_gpio_irq_disable() local
398 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
399 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_disable()
400 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_disable()
401 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
409 u32 pin_reg; in amd_gpio_irq_mask() local
415 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
416 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_mask()
417 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
423 u32 pin_reg; in amd_gpio_irq_unmask() local
429 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
430 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_unmask()
431 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
437 u32 pin_reg; in amd_gpio_irq_set_wake() local
445 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_wake()
448 pin_reg |= wake_mask; in amd_gpio_irq_set_wake()
450 pin_reg &= ~wake_mask; in amd_gpio_irq_set_wake()
452 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_wake()
484 u32 pin_reg, pin_reg_irq_en, mask; in amd_gpio_irq_set_type() local
490 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
494 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
495 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
496 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
501 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
502 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
503 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
508 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
509 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
510 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
515 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
516 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
517 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
522 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
523 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
524 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
536 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; in amd_gpio_irq_set_type()
553 pin_reg_irq_en = pin_reg; in amd_gpio_irq_set_type()
559 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
725 u32 pin_reg; in amd_pinconf_get() local
732 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_get()
736 arg = pin_reg & DB_TMR_OUT_MASK; in amd_pinconf_get()
740 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
744 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
748 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; in amd_pinconf_get()
768 u32 pin_reg; in amd_pinconf_set() local
777 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_set()
785 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); in amd_pinconf_set()
786 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; in amd_pinconf_set()
790 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); in amd_pinconf_set()
791 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; in amd_pinconf_set()
795 pin_reg &= ~(DRV_STRENGTH_SEL_MASK in amd_pinconf_set()
797 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) in amd_pinconf_set()
807 writel(pin_reg, gpio_dev->base + pin*4); in amd_pinconf_set()
870 u32 pin_reg, mask; in amd_gpio_irq_init() local
885 pin_reg = readl(gpio_dev->base + pin * 4); in amd_gpio_irq_init()
886 pin_reg &= ~mask; in amd_gpio_irq_init()
887 writel(pin_reg, gpio_dev->base + pin * 4); in amd_gpio_irq_init()