36 #define ctrl_dbg(ctrl, format, arg...)					\  argument
37 	pci_dbg(ctrl->pci_dev, format, ## arg)
38 #define ctrl_err(ctrl, format, arg...)					\  argument
39 	pci_err(ctrl->pci_dev, format, ## arg)
40 #define ctrl_info(ctrl, format, arg...)					\  argument
41 	pci_info(ctrl->pci_dev, format, ## arg)
42 #define ctrl_warn(ctrl, format, arg...)					\  argument
43 	pci_warn(ctrl->pci_dev, format, ## arg)
58 	struct controller *ctrl;  member
140 int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
141 void shpchp_remove_ctrl_files(struct controller *ctrl);
144 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
145 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
146 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
147 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
150 void cleanup_slots(struct controller *ctrl);
152 int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
197 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)  in shpchp_find_slot()  argument
201 	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {  in shpchp_find_slot()
206 	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);  in shpchp_find_slot()
215 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);  in amd_pogo_errata_save_misc_reg()
217 	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;  in amd_pogo_errata_save_misc_reg()
225 	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);  in amd_pogo_errata_save_misc_reg()
237 …pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_r…  in amd_pogo_errata_restore_misc_reg()
240 		ctrl_dbg(p_slot->ctrl,  in amd_pogo_errata_restore_misc_reg()
244 		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);  in amd_pogo_errata_restore_misc_reg()
248 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);  in amd_pogo_errata_restore_misc_reg()
251 		ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");  in amd_pogo_errata_restore_misc_reg()
253 		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);  in amd_pogo_errata_restore_misc_reg()
256 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);  in amd_pogo_errata_restore_misc_reg()
258 	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
263 	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
268 	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
273 	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
278 	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
282 	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);  in amd_pogo_errata_restore_misc_reg()
300 void shpchp_release_ctlr(struct controller *ctrl);
301 int shpchp_check_cmd_status(struct controller *ctrl);