124 	unsigned int res, bit, ctrl;  in dw_pci_bottom_mask()  local
129 	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;  in dw_pci_bottom_mask()
130 	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;  in dw_pci_bottom_mask()
133 	pp->irq_mask[ctrl] |= BIT(bit);  in dw_pci_bottom_mask()
134 	dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);  in dw_pci_bottom_mask()
143 	unsigned int res, bit, ctrl;  in dw_pci_bottom_unmask()  local
148 	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;  in dw_pci_bottom_unmask()
149 	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;  in dw_pci_bottom_unmask()
152 	pp->irq_mask[ctrl] &= ~BIT(bit);  in dw_pci_bottom_unmask()
153 	dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);  in dw_pci_bottom_unmask()
162 	unsigned int res, bit, ctrl;  in dw_pci_bottom_ack()  local
164 	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;  in dw_pci_bottom_ack()
165 	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;  in dw_pci_bottom_ack()
255 	u32 ctrl;  in dw_pcie_free_msi()  local
257 	for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {  in dw_pcie_free_msi()
258 		if (pp->msi_irq[ctrl] > 0)  in dw_pcie_free_msi()
259 			irq_set_chained_handler_and_data(pp->msi_irq[ctrl],  in dw_pcie_free_msi()
285 	u32 ctrl, max_vectors;  in dw_pcie_parse_split_msi_irq()  local
289 	for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {  in dw_pcie_parse_split_msi_irq()
292 		msi_name[3] = '0' + ctrl;  in dw_pcie_parse_split_msi_irq()
301 		pp->msi_irq[ctrl] = irq;  in dw_pcie_parse_split_msi_irq()
305 	if (ctrl == 0)  in dw_pcie_parse_split_msi_irq()
308 	max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;  in dw_pcie_parse_split_msi_irq()
327 	u32 ctrl, num_ctrls;  in dw_pcie_msi_host_init()  local
329 	for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)  in dw_pcie_msi_host_init()
330 		pp->irq_mask[ctrl] = ~0;  in dw_pcie_msi_host_init()
359 	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {  in dw_pcie_msi_host_init()
360 		if (pp->msi_irq[ctrl] > 0)  in dw_pcie_msi_host_init()
361 			irq_set_chained_handler_and_data(pp->msi_irq[ctrl],  in dw_pcie_msi_host_init()
834 	u32 val, ctrl, num_ctrls;  in dw_pcie_setup_rc()  local
849 		for (ctrl = 0; ctrl < num_ctrls; ctrl++) {  in dw_pcie_setup_rc()
851 					    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),  in dw_pcie_setup_rc()
852 					    pp->irq_mask[ctrl]);  in dw_pcie_setup_rc()
854 					    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),  in dw_pcie_setup_rc()