61 static void vsc8584_macsec_phy_write(struct phy_device *phydev,  in vsc8584_macsec_phy_write()  function
100 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,  in vsc8584_macsec_classification()
117 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,  in vsc8584_macsec_flow_default_action()
134 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,  in vsc8584_macsec_flow_default_action()
166 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,  in vsc8584_macsec_integrity_checks()
169 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,  in vsc8584_macsec_integrity_checks()
181 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,  in vsc8584_macsec_block_init()
186 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,  in vsc8584_macsec_block_init()
189 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,  in vsc8584_macsec_block_init()
191 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,  in vsc8584_macsec_block_init()
198 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);  in vsc8584_macsec_block_init()
201 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,  in vsc8584_macsec_block_init()
204 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);  in vsc8584_macsec_block_init()
208 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);  in vsc8584_macsec_block_init()
211 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,  in vsc8584_macsec_block_init()
216 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),  in vsc8584_macsec_block_init()
223 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);  in vsc8584_macsec_block_init()
225 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,  in vsc8584_macsec_block_init()
238 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,  in vsc8584_macsec_block_init()
252 		vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);  in vsc8584_macsec_mac_init()
259 	vsc8584_macsec_phy_write(phydev, bank,  in vsc8584_macsec_mac_init()
265 	vsc8584_macsec_phy_write(phydev, bank,  in vsc8584_macsec_mac_init()
278 	vsc8584_macsec_phy_write(phydev, bank,  in vsc8584_macsec_mac_init()
281 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,  in vsc8584_macsec_mac_init()
294 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);  in vsc8584_macsec_mac_init()
299 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);  in vsc8584_macsec_mac_init()
301 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,  in vsc8584_macsec_mac_init()
309 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);  in vsc8584_macsec_mac_init()
311 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,  in vsc8584_macsec_mac_init()
330 	vsc8584_macsec_phy_write(phydev, FC_BUFFER,  in __vsc8584_macsec_init()
339 	vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val);  in __vsc8584_macsec_init()
341 	vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG,  in __vsc8584_macsec_init()
351 	vsc8584_macsec_phy_write(phydev, FC_BUFFER,  in __vsc8584_macsec_init()
356 	vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);  in __vsc8584_macsec_init()
364 	vsc8584_macsec_phy_write(phydev, proc_bank,  in __vsc8584_macsec_init()
394 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),  in vsc8584_macsec_flow()
396 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),  in vsc8584_macsec_flow()
403 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),  in vsc8584_macsec_flow()
409 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);  in vsc8584_macsec_flow()
410 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);  in vsc8584_macsec_flow()
445 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);  in vsc8584_macsec_flow()
472 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));  in vsc8584_macsec_flow_enable()
477 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);  in vsc8584_macsec_flow_enable()
487 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));  in vsc8584_macsec_flow_disable()
492 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);  in vsc8584_macsec_flow_disable()
555 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),  in vsc8584_macsec_transformation()
559 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),  in vsc8584_macsec_transformation()
564 		vsc8584_macsec_phy_write(phydev, bank,  in vsc8584_macsec_transformation()
570 		vsc8584_macsec_phy_write(phydev, bank,  in vsc8584_macsec_transformation()
575 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),  in vsc8584_macsec_transformation()
581 		vsc8584_macsec_phy_write(phydev, bank,  in vsc8584_macsec_transformation()
587 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),  in vsc8584_macsec_transformation()
589 	vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),  in vsc8584_macsec_transformation()
593 		vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),  in vsc8584_macsec_transformation()
1008 	vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_AIC_CTRL, 0xf);  in vsc8584_config_macsec_intr()
1009 	vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_INTR_CTRL_STATUS,  in vsc8584_config_macsec_intr()