22 static u32 vsc8584_macsec_phy_read(struct phy_device *phydev,  in vsc8584_macsec_phy_read()  function
162 	val = vsc8584_macsec_phy_read(phydev, bank,  in vsc8584_macsec_integrity_checks()
196 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);  in vsc8584_macsec_block_init()
206 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);  in vsc8584_macsec_block_init()
221 		val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);  in vsc8584_macsec_block_init()
254 	val = vsc8584_macsec_phy_read(phydev, bank,  in vsc8584_macsec_mac_init()
262 	val = vsc8584_macsec_phy_read(phydev, bank,  in vsc8584_macsec_mac_init()
268 	val = vsc8584_macsec_phy_read(phydev, bank,  in vsc8584_macsec_mac_init()
292 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);  in vsc8584_macsec_mac_init()
296 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);  in vsc8584_macsec_mac_init()
307 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);  in vsc8584_macsec_mac_init()
335 	val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG);  in __vsc8584_macsec_init()
345 	val = vsc8584_macsec_phy_read(phydev, FC_BUFFER,  in __vsc8584_macsec_init()
354 	val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG);  in __vsc8584_macsec_init()
360 	val = vsc8584_macsec_phy_read(phydev, proc_bank,  in __vsc8584_macsec_init()
475 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));  in vsc8584_macsec_flow_enable()
490 	val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));  in vsc8584_macsec_flow_disable()
979 	cause = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,  in vsc8584_handle_macsec_interrupt()
992 		val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,  in vsc8584_handle_macsec_interrupt()