415 	u32 lval1, lval2, i;  in rts5264_init_from_hw()  local
439 	pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval2);  in rts5264_init_from_hw()
440 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);  in rts5264_init_from_hw()
442 	valid = (u8)((lval2 >> 16) & 0x03);  in rts5264_init_from_hw()
466 	pci_read_config_dword(pdev, setting_reg2, &lval2);  in rts5264_init_from_hw()
467 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);  in rts5264_init_from_hw()
469 	if (!rts5264_vendor_setting_valid(lval2)) {  in rts5264_init_from_hw()
474 	pcr->rtd3_en = rts5264_reg_to_rtd3(lval2);  in rts5264_init_from_hw()
476 	if (rts5264_reg_check_reverse_socket(lval2))  in rts5264_init_from_hw()
492 		rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));  in rts5264_init_from_hw()
493 		rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));  in rts5264_init_from_hw()
494 		rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));  in rts5264_init_from_hw()
497 		lval2 = lval2 & 0x00FFFFFF;  in rts5264_init_from_hw()
498 		pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2);  in rts5264_init_from_hw()