Lines Matching refs:mmio_base
53 u32 mmio_base; member
63 .mmio_base = RENDER_RING_BASE,
71 .mmio_base = BLT_RING_BASE,
79 .mmio_base = XEHPC_BCS1_RING_BASE,
87 .mmio_base = XEHPC_BCS2_RING_BASE,
95 .mmio_base = XEHPC_BCS3_RING_BASE,
103 .mmio_base = XEHPC_BCS4_RING_BASE,
111 .mmio_base = XEHPC_BCS5_RING_BASE,
119 .mmio_base = XEHPC_BCS6_RING_BASE,
127 .mmio_base = XEHPC_BCS7_RING_BASE,
135 .mmio_base = XEHPC_BCS8_RING_BASE,
144 .mmio_base = BSD_RING_BASE,
152 .mmio_base = BSD2_RING_BASE,
160 .mmio_base = BSD3_RING_BASE,
168 .mmio_base = BSD4_RING_BASE,
176 .mmio_base = XEHP_BSD5_RING_BASE,
184 .mmio_base = XEHP_BSD6_RING_BASE,
192 .mmio_base = XEHP_BSD7_RING_BASE,
200 .mmio_base = XEHP_BSD8_RING_BASE,
208 .mmio_base = VEBOX_RING_BASE,
216 .mmio_base = VEBOX2_RING_BASE,
224 .mmio_base = XEHP_VEBOX3_RING_BASE,
232 .mmio_base = XEHP_VEBOX4_RING_BASE,
240 .mmio_base = COMPUTE0_RING_BASE,
248 .mmio_base = COMPUTE1_RING_BASE,
256 .mmio_base = COMPUTE2_RING_BASE,
264 .mmio_base = COMPUTE3_RING_BASE,
271 .mmio_base = GSCCS_RING_BASE,
298 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); in xe_hw_engine_mmio_write32()
301 reg.addr += hwe->mmio_base; in xe_hw_engine_mmio_write32()
318 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); in xe_hw_engine_mmio_read32()
321 reg.addr += hwe->mmio_base; in xe_hw_engine_mmio_read32()
511 hwe->mmio_base = info->mmio_base; in hw_engine_init_early()
579 idledly = xe_mmio_read32(>->mmio, RING_IDLEDLY(hwe->mmio_base)); in adjust_idledly()
580 maxcnt = xe_mmio_read32(>->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base)); in adjust_idledly()
592 xe_mmio_write32(>->mmio, RING_IDLEDLY(hwe->mmio_base), idledly); in adjust_idledly()
893 snapshot->mmio_base = hwe->mmio_base; in xe_hw_engine_snapshot_capture()
1017 return xe_mmio_read64_2x32(&hwe->gt->mmio, RING_TIMESTAMP(hwe->mmio_base)); in xe_hw_engine_read_timestamp()