55 	value = tegra_dc_readl(dc, offset);  in tegra_dc_readl_active()
87 	return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));  in tegra_plane_readl()
958 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in __tegra_cursor_atomic_update()
962 	value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);  in __tegra_cursor_atomic_update()
1023 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
1085 		(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);  in tegra_cursor_atomic_async_update()
1089 		(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);  in tegra_cursor_atomic_async_update()
1656 			   offset, tegra_dc_readl(dc, offset));  in tegra_dc_show_regs()
1685 	value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);  in tegra_dc_show_crc()
1780 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
1792 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
1960 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
2122 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_disable()
2249 		value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_atomic_enable()
2254 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_atomic_enable()
2260 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_enable()
2315 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
2319 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
2532 	status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);  in tegra_dc_irq()