2801 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;  in evergreen_dma_cs_parse()  local
2856 			r = r600_dma_cs_next_reloc(p, &src_reloc);  in evergreen_dma_cs_parse()
2874 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2876 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2885 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2887 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2897 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
2907 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2908 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2914 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2916 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2933 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2935 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2944 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);  in evergreen_dma_cs_parse()
2946 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2956 				ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);  in evergreen_dma_cs_parse()
2957 				ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2977 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2979 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2994 				ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2997 				ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3017 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3019 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3034 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3035 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3048 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3054 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3055 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3079 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3081 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3096 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3097 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3108 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3118 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3119 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3125 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3127 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3144 				ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3166 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3168 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3183 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
3184 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()