520 	(s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
666 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,  in find_cmd_entry()  argument
671 	hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {  in find_cmd_entry()
680 get_cmd_info(struct intel_gvt *gvt, u32 cmd,  in get_cmd_info()  argument
689 	return find_cmd_entry(gvt, opcode, engine);  in get_cmd_info()
896 	struct intel_gvt *gvt = vgpu->gvt;  in cmd_reg_handler()  local
900 	if (offset + 4 > gvt->device_info.mmio_size) {  in cmd_reg_handler()
909 		intel_gvt_mmio_set_cmd_accessible(gvt, offset);  in cmd_reg_handler()
910 		mmio_info = intel_gvt_find_mmio_info(gvt, offset);  in cmd_reg_handler()
912 			intel_gvt_mmio_set_cmd_write_patch(gvt, offset);  in cmd_reg_handler()
916 	if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) {  in cmd_reg_handler()
926 		    (IS_BROADWELL(gvt->gt->i915) &&  in cmd_reg_handler()
938 		if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)  in cmd_reg_handler()
972 	if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) {  in cmd_reg_handler()
978 		mmio_info = intel_gvt_find_mmio_info(gvt, offset);  in cmd_reg_handler()
1015 	    intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&  in cmd_reg_handler()
1023 			if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))  in cmd_reg_handler()
1095 	struct intel_gvt *gvt = s->vgpu->gvt;  in cmd_handler_lrm()  local
1096 	int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_lrm()
1124 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_srm()
1182 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_pipe_control()
1542 	int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in get_gma_bb_from_cmd()
1563 	u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;  in cmd_address_audit()
1607 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_mi_store_data_imm()
1664 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_mi_op_2f()
1714 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_mi_flush_dw()
1834 	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);  in find_bb_size()
1846 		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);  in find_bb_size()
1880 	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);  in audit_bb_end()
2721 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)  in add_cmd_entry()  argument
2723 	hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);  in add_cmd_entry()
2740 		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);  in cmd_parser_exec()
3108 	struct intel_gvt *gvt = vgpu->gvt;  in intel_gvt_update_reg_whitelist()  local
3112 	if (gvt->is_reg_whitelist_updated)  in intel_gvt_update_reg_whitelist()
3116 	for_each_engine(engine, gvt->gt, id) {  in intel_gvt_update_reg_whitelist()
3157 	gvt->is_reg_whitelist_updated = true;  in intel_gvt_update_reg_whitelist()
3212 static int init_cmd_table(struct intel_gvt *gvt)  in init_cmd_table()  argument
3214 	unsigned int gen_type = intel_gvt_get_device_type(gvt);  in init_cmd_table()
3232 		add_cmd_entry(gvt, e);  in init_cmd_table()
3241 static void clean_cmd_table(struct intel_gvt *gvt)  in clean_cmd_table()  argument
3247 	hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)  in clean_cmd_table()
3250 	hash_init(gvt->cmd_table);  in clean_cmd_table()
3253 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)  in intel_gvt_clean_cmd_parser()  argument
3255 	clean_cmd_table(gvt);  in intel_gvt_clean_cmd_parser()
3258 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)  in intel_gvt_init_cmd_parser()  argument
3262 	ret = init_cmd_table(gvt);  in intel_gvt_init_cmd_parser()
3264 		intel_gvt_clean_cmd_parser(gvt);  in intel_gvt_init_cmd_parser()